VMULPS

VMULPS is MULPS in VEX and EVEX encodings; the MULPS page covers MXCSR, denormals and the FTZ and DAZ bits. The encodings add what VADDPS shows: a separate destination, the bits above the result cleared, and in EVEX a write mask, a broadcast single and a rounding mode given in the instruction. Under {rn-sae}, with the underflow and invalid exceptions unmasked, Zen 5 multiplied the smallest normal single by 0.5 to the denormal 2^-127 and quieted a signaling NaN in another element, without #XM and without changing MXCSR.

Contraction into FMA#

What changes most in practice is that a multiplication followed by an addition may not compile to VMULPS at all. The x86-64-v3 level includes FMA, and a fused multiply-add rounds once where VMULPS and VADDPS round twice. For a[i] = b[i] * c[i] + d[i] over floats, GCC 14 and Clang 23 at -O2 emit MULPS and ADDPS for the baseline, but one VFMADD132PS (GCC) or VFMADD213PS (Clang) per vector with -march=x86-64-v3, so the two builds of the same source can differ in the last bit. How far they go differs:

• GCC fuses by default, even across statements (t = b[i] * c[i]; a[i] = t + d[i];), but not with an ISO dialect such as -std=c17.
• Clang fuses only within one expression, whatever the dialect: the two-statement version keeps VMULPS and VADDPS.
• With -ffp-contract=off, both keep VMULPS and VADDPS.

Pipes on Zen 5#

AMD’s Zen 5 guide lists VMULPS as one macro-op with a latency of 3 cycles at every width. It runs on pipes 0 and 1, which also do the fused multiply-adds, compares and variable blends, while additions go to pipes 2 and 3 (Section 2.11.1), so a loop with as many multiplications as additions can keep all four busy.

In the optimization guide

What the optimization guide says about VMULPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• What Broadwell changed: Broadwell cuts the latency of floating-point multiplication from 5 cycles to 3, for SSE and AVX code and, by Intel’s manual, x87 as well; FMA stays at 5. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = mul(a, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMULPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR

All 253 AVX instructions

More AVX10.1 instructions

• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW

All 686 AVX10.1 instructions