VMULSD instruction (AVX, AVX10.1)

VMULSD is MULSD in VEX and EVEX encodings: the product of the low doubles of its two sources, with the high double copied from the first source and the bits above 127 cleared. The MULSD page covers Horner’s rule and what FMA changes in it, VMULSS where a product survives once FMA is available, and VADDSS what the encodings change. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

An exact product of two floats

A single has a 24-bit significand, so the product of two singles needs at most 48 bits and fits a double’s 53 exactly. (double)a * b with float a and b is therefore the exact product: in our builds with -march=x86-64-v3 or x86-64-v4, GCC 14 and Clang 23 at -O2 widen both with VCVTSS2SD, each in place (vcvtss2sd xmm0, xmm0, xmm0), and multiply with VMULSD. The double’s wider exponent range also rules out the overflow and underflow that the same product can meet as a float.

On Zen 5

vmulsd xmm7, xmm11, qword ptr [mem], under MXCSR 7F80H (round toward zero), multiplied -1 by -0 and gave +0: the sign of a zero product follows the signs of the factors, whatever the rounding.
vmulsd xmm7{k4}, xmm12, xmm7, {rd-sae}, with bit 0 of K4 set, multiplied the quiet NaN 7FF8000000012345H by 1 and returned it, with the high double, 1, from XMM12 rather than XMM7, whose high double was that NaN.
vmulsd xmm0{k7}{z}, xmm31, qword ptr [mem], with bit 0 of K7 set, gave 1 times 0 as +0 and took the high double, -1, from XMM31.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows 3 cycles on pipes FP0 and FP1, the figures of MULSD.

Forms

Every encoding of VMULSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMULSD xmm, xmm, m64` VMULSD_XMMdq_XMMdq_MEMq	`VEX.LIG.F2.0F.WIG 59 /r`	AVX
`VMULSD xmm, xmm, xmm` VMULSD_XMMdq_XMMdq_XMMq	`VEX.LIG.F2.0F.WIG 59 /r`	AVX
`VMULSD xmm {k}{z}, xmm, xmm, {er}` VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512	`EVEX.LIG.F2.0F.W1 59 /r`	AVX10.1 or AVX512F
`VMULSD xmm {k}{z}, xmm, m64` VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512	`EVEX.LIG.F2.0F.W1 59 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, m64` `xmm {k}{z}, xmm, m64`	`xmm, xmm, xmm` `xmm {k}{z}, xmm, xmm, {er}`
Sandy Bridge	11 / 1p0	5 / 1p0
Haswell	10 / 0.5p01	5 / 0.5p01
Broadwell	8 / 0.5p01	3 / 0.5p01
Skylake, Skylake-SP, Ice Lake	9 / 0.5p01	4 / 0.5p01
Alder Lake, Sapphire Rapids	11 / 0.5p01	4 / 0.5p01
Lunar Lake	9 / 2V0 V1	3 / 1.5V0 V1
Piledriver	10 / 1.5FPFMA FPU1	5 / 1FPFMA FPU1
Zen	11 / 0.5FPU0 FPU1	4 / 0.5FPU0 FPU1
Zen 2	10 / 0.5FPU0 FPU1	3 / 0.5FPU0 FPU1
Zen 3, Zen 4	10 / 0.5FP0 FP1	3 / 0.5FP0 FP1
Jaguar	9 / 2FPM FPU1	4 / 2FPM FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm2.

The write mask k1 applies to the low double: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result double 0 is computed from double 0 of xmm2 and xmm3; double 1 is that of xmm2. Result doubles 1 to 0: a1, a0×b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = mul(a, b)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMULSD xmm, xmm, xmm/m64`
`xmm`	explicit	write
`xmm`	explicit	read
`xmm/m64`	explicit	read
`VMULSD xmm {k}{z}, xmm, xmm/m64, {er}`
`xmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-3
EVEX forms: AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
EVEX forms: write masking
EVEX memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMULSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mul_round_sd` `__m128d _mm_mul_round_sd(__m128d A, __m128d B, const int R)`	`VMULSD xmm, xmm, xmm, {er}` EVEX.LIG -mavx512f
`_mm_mul_sd` `__m128d _mm_mul_sd(__m128d __a, __m128d __b)`	`VMULSD xmm, xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_mask_mul_round_sd` `__m128d _mm_mask_mul_round_sd(__m128d W, __mmask8 U, __m128d A, __m128d B, const int R)`	`VMULSD xmm {k}, xmm, xmm, {er}` EVEX.LIG -mavx512f
`_mm_mask_mul_sd` `__m128d _mm_mask_mul_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)`	`VMULSD xmm {k}, xmm, xmm` EVEX.LIG -mavx512f
`_mm_maskz_mul_round_sd` `__m128d _mm_maskz_mul_round_sd(__mmask8 U, __m128d A, __m128d B, const int R)`	`VMULSD xmm {k}{z}, xmm, xmm, {er}` EVEX.LIG -mavx512f
`_mm_maskz_mul_sd` `__m128d _mm_maskz_mul_sd(__mmask8 __U, __m128d __A, __m128d __B)`	`VMULSD xmm {k}{z}, xmm, xmm` EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

An exact product of two floats#

On Zen 5#