VMULSH

VMULSH multiplies the low halves of its two sources and rounds the product once, under MXCSR.RC or, between registers, under a rounding mode given in the instruction ({er}). Bits 127:16 come from the first source and the bits above 127 are cleared, as VMULSS does for singles. It is the scalar form of VMULPH, whose page shows how early a square overflows in half precision, and is opcode 59h with the F3 prefix in EVEX map 5. Being EVEX-only, it takes a write mask on the one element and xmm16 to xmm31, and reads two bytes when its second source is in memory. It reports invalid, overflow, underflow, precision and denormal. VADDPH covers the format, the CPUID bits and FP16’s use of MXCSR; VDIVSH divides.

Where compilers use it#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile x * y and x * x on _Float16 values to one VMULSH, and x * 2 to vaddsh xmm0, xmm0, xmm0, as VMULPH’s page shows for arrays. The type of a constant matters: x * (_Float16)0.1f is a VMULSH with the half read from memory, while x * 0.1f multiplies in single precision, since C converts the half to float first, and costs a VCVTSH2SS, a VMULSS and a VCVTSS2SH. The other way round, a function that returns x * y as a float multiplies in half precision with VMULSH and widens the rounded product afterwards.

A product over a _Float16 array keeps C’s order of operations, so both compilers chain VMULSH with each half read from memory, GCC unrolled twice and Clang eight times; only -ffast-math lets GCC multiply 32 halves at a time with VMULPH and combine them at the end. Such a product overflows to infinity or underflows to zero after few factors, since halves reach only 65504 and go down, as denormals, to about 6e-8 (Intel’s optimization manual, Section 18.5.2).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VMULSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = mul(a, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMULSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR

All 686 AVX10.1 instructions