VMULSS

VMULSS is MULSS in VEX and EVEX encodings: the product of the low singles of its two sources, with singles 1 to 3 copied from the first source and the bits above 127 cleared. The MULSS page shows how constants and powf compile, and VADDSS what the encodings change. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

Where the FMA takes over#

The levels x86-64-v3 and x86-64-v4 include FMA, and GCC 14 and Clang 23 contract a product that feeds a sum. So in our builds at -O2 with -march=x86-64-v3 or x86-64-v4, the dot product fa[0]*fb[0] + fa[1]*fb[1] + fa[2]*fb[2] over global arrays has a single VMULSS, for the product of the second pair, and adds the other two with VFMADD231SS, each rounding once. The x86-64 baseline computes three MULSS and two ADDSS, so the two builds can differ in the last bit. VMULSS remains where nothing is added to the product.

On Zen 5#

• vmulss xmm24{k7}{z}, xmm3, dword ptr [mem], with bit 0 of K7 set and MXCSR at FFC0H (FTZ and DAZ set), squared the smallest denormal and gave +0 with no flag: DAZ read it as zero. MULSS’s page squares a denormal with both clear, which sets UE, PE and DE, and cites AMD’s advice to set the two for speed.
• vmulss xmm1, xmm2, xmm3, under 3FC0H, gave -0 for -0 times +0, while XMM2’s upper singles, signaling NaNs among them, came through unchanged without IE.
• vmulss xmm12, xmm6, dword ptr [mem], under 7F80H, multiplied the quiet NaN 7FC00000H by FFC00000H and returned the first source’s NaN.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows 3 cycles on pipes FP0 and FP1, as for MULSS. VMULSD is the double form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = mul(a, b)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMULSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN

All 253 AVX instructions

More AVX10.1 instructions

• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD

All 686 AVX10.1 instructions