VORPD

VORPD is ORPD in VEX and EVEX encodings: the bitwise OR of two vectors read as doubles, nothing rounded and MXCSR left alone. VORPS covers what the OR is for. The VEX forms, xmm and ymm, need AVX; the EVEX forms need AVX512DQ (with AVX512VL below 512 bits) or AVX10.1, not AVX512F alone, and add a write mask per double and a second source of one broadcast double. Every form writes a separate destination, reads memory at any alignment and zeroes the register above the vector length.

Recorded on Zen 5#

Under MXCSR 1F80H, without a flag set:

• vorpd zmm5{k6}, zmm5, qword bcst [mem] ORed the smallest denormal into elements 2, 5 and 7, the ones k6 selects: -0.0 became 8000000000000001h, the negative smallest denormal; the other five elements kept their values.
• vorpd ymm14{k4}{z}, ymm8, ymm29 wrote -0.0, from -0.0 OR -0.0 and +0.0 OR -0.0, into elements 0 and 2, and zeroed elements 1 and 3, which k4 leaves out, as well as the bits above 255.

In compiled code#

In our builds at -O2 over global double arrays with -march=x86-64-v3:

• -fabs(b[i]) is VANDNPD and VORPD with the same -0.0 in GCC 14, and a single VORPS with -0.0 in Clang 23.
• For ((b[i] < c[i]) | (b[i] > d[i])) ? 0.0 : b[i], Clang ORs the two VCMPLTPD results with VORPD and clears the selected elements with VANDNPD; GCC uses VPOR and VBLENDVPD.

With -march=x86-64-v4, those compares write mask registers that KORB (GCC) or KORW (Clang) combines, and GCC’s -fabs becomes one VPTERNLOGQ. Clang spells _mm512_or_pd as VORPS but keeps VORPD for a broadcast, vorpd zmm0, zmm0, qword bcst [rdi], where GCC loads the double with VBROADCASTSD first.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike one macro-op with a latency of 1 cycle on pipes FP0 to FP3, four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = zmm2.q[i] | src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VORPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB

All 253 AVX instructions

More AVX10.1 instructions

• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND

All 686 AVX10.1 instructions