x86-64.net

Instruction

VORPS

Computes the bitwise OR of packed singles.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VORPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VORPS xmm, xmm, m128 VORPS_XMMdq_XMMdq_MEMdqVEX.128.NP.0F.WIG 56 /rAVX
VORPS xmm, xmm, xmm VORPS_XMMdq_XMMdq_XMMdqVEX.128.NP.0F.WIG 56 /rAVX
VORPS ymm, ymm, m256 VORPS_YMMqq_YMMqq_MEMqqVEX.256.NP.0F.WIG 56 /rAVX
VORPS ymm, ymm, ymm VORPS_YMMqq_YMMqq_YMMqqVEX.256.NP.0F.WIG 56 /rAVX
VORPS xmm {k}{z}, xmm, xmm VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.NP.0F.W0 56 /rAVX10.1 or AVX512DQ + AVX512VL
VORPS xmm {k}{z}, xmm, m128/m32bcst VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.NP.0F.W0 56 /rAVX10.1 or AVX512DQ + AVX512VL
VORPS ymm {k}{z}, ymm, ymm VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512EVEX.256.NP.0F.W0 56 /rAVX10.1 or AVX512DQ + AVX512VL
VORPS ymm {k}{z}, ymm, m256/m32bcst VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.NP.0F.W0 56 /rAVX10.1 or AVX512DQ + AVX512VL
VORPS zmm {k}{z}, zmm, zmm VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512EVEX.512.NP.0F.W0 56 /rAVX10.1 or AVX512DQ
VORPS zmm {k}{z}, zmm, m512/m32bcst VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.NP.0F.W0 56 /rAVX10.1 or AVX512DQ

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VORPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_or_ps __m128 _mm_or_ps(__m128 __a, __m128 __b)

VORPS xmm, xmm, xmm VEX.128 -mavxwith AVX enabled; Clang emits the equivalent VPOR

_mm256_or_ps __m256 _mm256_or_ps(__m256 __a, __m256 __b)

VORPS ymm, ymm, ymm VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512DQ_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.