VORPS

VORPS computes the bitwise OR of two vectors of singles, in the VEX form with a separate destination and up to 256 bits, in the EVEX form, which needs AVX512DQ, with masking and a broadcast single as well. Like VANDPS, whose page covers the family’s masks for floats, it sees only bits: MXCSR plays no part and NaNs pass through. Two uses are its own.

Setting the sign bit#

An OR with -0.0, whose only set bit is the sign, makes every element negative: a[i] = -fabsf(b[i]). Clang 23 at -O2 with -march=x86-64-v3 compiles that loop to one VORPS with -0.0 broadcast and the data straight from memory. GCC 14 follows the C expression literally: a VANDNPS with -0.0 clears the sign bits for fabsf, then a VORPS with the same constant sets them again.

Combining compares#

A compare such as VCMPPS gives all ones or all zeros per element, and an OR of two such results is a logical or. For ((b[i] < c[i]) | (b[i] > d[i])) ? 0.0f : b[i] with -march=x86-64-v3, Clang combines the two VCMPLTPS results with VORPS and zeroes the selected elements with VANDNPS; GCC combines them with the integer VPOR and selects with VBLENDVPS. The bits are the same, but AMD’s Zen 5 guide asks for consistent data types among the instructions that work on the same data, keeping single-precision operations on the results of single-precision ones (Section 2.11.2). With -march=x86-64-v4 neither compiler uses a vector OR at all: the compares write mask registers, KORW or KORB combines them, and a masked move does the select.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm2.d[i] | src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VORPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW

All 253 AVX instructions

More AVX10.1 instructions

• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ

All 686 AVX10.1 instructions