Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VP2INTERSECTD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VP2INTERSECTD k+1, xmm, xmm VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.F2.0F38.W0 68 /rAVX512_VP2INTERSECT + AVX512VL
VP2INTERSECTD k+1, xmm, m128/m32bcst VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.F2.0F38.W0 68 /rAVX512_VP2INTERSECT + AVX512VL
VP2INTERSECTD k+1, ymm, ymm VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512EVEX.256.F2.0F38.W0 68 /rAVX512_VP2INTERSECT + AVX512VL
VP2INTERSECTD k+1, ymm, m256/m32bcst VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.F2.0F38.W0 68 /rAVX512_VP2INTERSECT + AVX512VL
VP2INTERSECTD k+1, zmm, zmm VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512EVEX.512.F2.0F38.W0 68 /rAVX512_VP2INTERSECT
VP2INTERSECTD k+1, zmm, m512/m32bcst VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.F2.0F38.W0 68 /rAVX512_VP2INTERSECT

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = b = 0
for i in range(VL // 32):
    for j in range(VL // 32):
        if zmm2.d[i] == src3.d[j]:
            a |= 1 << i          # zmm2.d[i] is in src3
            b |= 1 << j          # src3.d[j] is in zmm2
k1.group[0].write(a)             # the even register
k1.group[1].write(b)             # the odd one after it
# m32bcst: src3.d[j] is the m32 for every j

Run on AMD Zen 5 (EPYC 9645): 14 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VP2INTERSECTD k+1, xmm, xmm/m128/m32bcst VP2INTERSECTD k+1, ymm, ymm/m256/m32bcst VP2INTERSECTD k+1, zmm, zmm/m512/m32bcst
k+1explicitwrite
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

Memory forms
embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VP2INTERSECTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_2intersect_epi32 void _mm_2intersect_epi32(__m128i __a, __m128i __b, __mmask8 *__m0, __mmask8 *__m1)

VP2INTERSECTD k+1, xmm, xmm EVEX.128 -mavx512vl -mavx512vp2intersect

_mm256_2intersect_epi32 void _mm256_2intersect_epi32(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 *__m1)

VP2INTERSECTD k+1, ymm, ymm EVEX.256 -mavx512vl -mavx512vp2intersect

_mm512_2intersect_epi32 void _mm512_2intersect_epi32(__m512i __a, __m512i __b, __mmask16 *__m0, __mmask16 *__m1)

VP2INTERSECTD k+1, zmm, zmm EVEX.512 -mavx512vp2intersect

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512_VP2INTERSECT_128

AVX512_VP2INTERSECT + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[8] AVX512_VP2INTERSECT
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Tiger Lake, Zen 5, Zen 6
AVX512_VP2INTERSECT_256

AVX512_VP2INTERSECT + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[8] AVX512_VP2INTERSECT
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Tiger Lake, Zen 5, Zen 6
AVX512_VP2INTERSECT_512

AVX512_VP2INTERSECT
CPUID.(EAX=07H,ECX=0):EDX[8] AVX512_VP2INTERSECT

Tiger Lake, Zen 5, Zen 6

More AVX512-VP2INTERSECT instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-433 (VP2INTERSECTD/VP2INTERSECTQ)
  5. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.