Instruction
VP2INTERSECTQ
Compares every quadword of one vector with every one of another and marks the elements that have a match in a pair of mask registers.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VP2INTERSECTQ k+1, xmm, xmm
VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 | EVEX.128.F2.0F38.W1 68 /r | AVX512_VP2INTERSECT + AVX512VL |
VP2INTERSECTQ k+1, xmm, m128/m64bcst
VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 | EVEX.128.F2.0F38.W1 68 /r | AVX512_VP2INTERSECT + AVX512VL |
VP2INTERSECTQ k+1, ymm, ymm
VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 | EVEX.256.F2.0F38.W1 68 /r | AVX512_VP2INTERSECT + AVX512VL |
VP2INTERSECTQ k+1, ymm, m256/m64bcst
VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 | EVEX.256.F2.0F38.W1 68 /r | AVX512_VP2INTERSECT + AVX512VL |
VP2INTERSECTQ k+1, zmm, zmm
VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 | EVEX.512.F2.0F38.W1 68 /r | AVX512_VP2INTERSECT |
VP2INTERSECTQ k+1, zmm, m512/m64bcst
VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 | EVEX.512.F2.0F38.W1 68 /r | AVX512_VP2INTERSECT |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
a = b = 0
for i in range(VL // 64):
for j in range(VL // 64):
if zmm2.q[i] == src3.q[j]:
a |= 1 << i # zmm2.q[i] is in src3
b |= 1 << j # src3.q[j] is in zmm2
k1.group[0].write(a) # the even register
k1.group[1].write(b) # the odd one after it
# m64bcst: src3.q[j] is the m64 for every jRun on AMD Zen 5 (EPYC 9645): 14 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VP2INTERSECTQ k+1, xmm, xmm/m128/m64bcst VP2INTERSECTQ k+1, ymm, ymm/m256/m64bcst VP2INTERSECTQ k+1, zmm, zmm/m512/m64bcst | ||
k+1 | explicit | write |
xmm, ymm, zmm | explicit | read |
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- Memory forms
- embedded broadcast (tuple Full)
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VP2INTERSECTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_2intersect_epi64
void _mm_2intersect_epi64(__m128i __a, __m128i __b, __mmask8 *__m0, __mmask8 *__m1) |
|
_mm256_2intersect_epi64
void _mm256_2intersect_epi64(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 *__m1) |
|
_mm512_2intersect_epi64
void _mm512_2intersect_epi64(__m512i __a, __m512i __b, __mmask8 *__m0, __mmask8 *__m1) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512_VP2INTERSECT_128 | AVX512_VP2INTERSECT + AVX512VL | Tiger Lake, Zen 5, Zen 6 |
AVX512_VP2INTERSECT_256 | AVX512_VP2INTERSECT + AVX512VL | Tiger Lake, Zen 5, Zen 6 |
AVX512_VP2INTERSECT_512 | AVX512_VP2INTERSECT | Tiger Lake, Zen 5, Zen 6 |
More AVX512-VP2INTERSECT instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-433 (VP2INTERSECTD/
VP2INTERSECTQ) - Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.