VP4DPWSSD instruction (AVX512_4VNNIW)

Forms

Every encoding of VP4DPWSSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VP4DPWSSD zmm {k}{z}, zmm+3, m128` VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512	`EVEX.512.F2.0F38.W0 52 /r`	AVX512_4VNNIW

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 0)[3] >> 2 & 1:
    fault(UD)                    # CPUID: no AVX512-4VNNIW
for i in range(16):
    if k1[i]:                    # 1 without a write mask
        r = zmm1.sd[i]
        for j in range(4):       # zmm2+3, in turn
            a = zmm2.group[j]
            for h in range(2):   # words 2i and 2i + 1
                x = a.sw[2 * i + h]
                y = mem.sw[2 * j + h]
                r += x * y
        zmm1.d[i] = r            # wraps around
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 1 case. It ran where CPUID reported no AVX512-4VNNIW, and raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VP4DPWSSD zmm {k}{z}, zmm+3, m128`
`zmm`	explicit	read, write (masked)
`{k}`	explicit	read (write mask)
`zmm+3`	explicit	read
`m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms: write masking; memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_4VNNIW_512` AVX512_4VNNIW	AVX512_4VNNIW `CPUID.(EAX=07H,ECX=0):EDX[2]` AVX512_4VNNIW	Knights Mill

More AVX512_4VNNIW instructions

VP4DPWSSDS