x86-64.net

Instruction

VPABSB

Computes the absolute value of packed signed bytes.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPABSB replaces each signed byte with its absolute value: the VEX and EVEX form of PABSB, whose page covers the operation and the baseline code that does without it, while VPABSD’s page explains the most negative value. The source may come from memory at any alignment, and the destination is zeroed above the vector length. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms belong to AVX512BW and add masking and the 512-bit width, but no broadcast, which byte elements never have. On Zen 5, the recorded vpabsb ymm0, ymmword ptr [mem] turned FFh into 01h and kept 7Fh and 80h in either 128-bit lane, and vpabsb xmm1{k7}{z}, xmmword ptr [mem] wrote the absolute values only into the ten bytes k7 selects and zeroed the other six.

In compiled code

In our builds at -O2 over int8_t arrays, b[i] < 0 ? -b[i] : b[i] is one VPABSB per vector, reading memory directly, in GCC 14 and Clang 23 with -march=x86-64-v3 and -march=x86-64-v4.

  • Sums. s += abs(b[i]) takes VPABSB and then zero-extends the bytes, with VPMOVZXBW and VPMOVZXWD in GCC and VPMOVZXBD in Clang, so that 80h counts as 128, the correct magnitude of -128.
  • Absolute differences. For abs(b[i] - c[i]) over uint8_t stored as bytes, GCC widens to words and uses VPABSW, while Clang subtracts the unsigned minimum from the maximum, VPMAXUB, VPMINUB and VPSUBB, and needs no absolute value at all.
  • A condition. if (c[i]) a[i] = abs(b[i]) stays scalar in GCC at -v3 and becomes VPEXTRB stores under per-byte branches in Clang; at -v4 both compute VPABSB for every byte and store under a byte mask with VMOVDQU8.

AMD’s latency spreadsheet for Zen 5 gives VPABSB, VEX or EVEX, a latency of two cycles and two per cycle on pipes FP0 and FP3.

Forms

Every encoding of VPABSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPABSB xmm, m128 VPABSB_XMMdq_MEMdqVEX.128.66.0F38.WIG 1C /rAVX
VPABSB xmm, xmm VPABSB_XMMdq_XMMdqVEX.128.66.0F38.WIG 1C /rAVX
VPABSB ymm, m256 VPABSB_YMMqq_MEMqqVEX.256.66.0F38.WIG 1C /rAVX2
VPABSB ymm, ymm VPABSB_YMMqq_YMMqqVEX.256.66.0F38.WIG 1C /rAVX2
VPABSB xmm {k}{z}, xmm VPABSB_XMMi8_MASKmskw_XMMi8_AVX512EVEX.128.66.0F38.WIG 1C /rAVX10.1 or AVX512BW + AVX512VL
VPABSB xmm {k}{z}, m128 VPABSB_XMMi8_MASKmskw_MEMi8_AVX512EVEX.128.66.0F38.WIG 1C /rAVX10.1 or AVX512BW + AVX512VL
VPABSB ymm {k}{z}, ymm VPABSB_YMMi8_MASKmskw_YMMi8_AVX512EVEX.256.66.0F38.WIG 1C /rAVX10.1 or AVX512BW + AVX512VL
VPABSB ymm {k}{z}, m256 VPABSB_YMMi8_MASKmskw_MEMi8_AVX512EVEX.256.66.0F38.WIG 1C /rAVX10.1 or AVX512BW + AVX512VL
VPABSB zmm {k}{z}, zmm VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512EVEX.512.66.0F38.WIG 1C /rAVX10.1 or AVX512BW
VPABSB zmm {k}{z}, m512 VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512EVEX.512.66.0F38.WIG 1C /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m128
xmm {k}{z}, m128no mask		xmm, xmm
xmm {k}{z}, xmmno mask		ymm, m256
ymm {k}{z}, m256no mask		ymm, ymmxmm {k}{z}, xmmwith a mask, zeroingxmm {k}{z}, m128with a mask, zeroingymm {k}{z}, ymmno maskymm {k}{z}, ymmwith a mask, zeroingymm {k}{z}, m256with a mask, zeroingzmm {k}{z}, zmmno maskzmm {k}{z}, zmmwith a mask, zeroingzmm {k}{z}, m512no maskzmm {k}{z}, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p011 / 0.5p017 / 0.5p011 / 0.5p011 / 0.5p018 / 0.5p011 / 1p01 / 1p08 / 1p08 / 1p0
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p013 / 0.5p0111 / 0.5p011 / 0.5p013 / 0.5p0111 / 0.5p011 / 1p03 / 1p09 / 1p011 / 1p0
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1
Zen 48 / 0.5FP0 FP1 FP2 FP32 / 11FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP12 / 12FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.253FP0 FP1 FP2 FP31 / 0.253FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.54FP0 FP1 FP2 FP31 / 0.54FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1806; AMD 58455, row 1222).
  2. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1807; AMD 58455, row 371).
  3. Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1809; AMD 58455, row 371).
  4. Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1810; AMD 58455, row 371).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.
VPABSB: element by elementResult byte i comes from byte i of xmm2. Result bytes 7 to 0: |a7|, unchanged (bit 6 of k1 is 0), |a5|, |a4|, |a3|, |a2|, |a1|, |a0|.…01234567xmm2or m128a11111110k1…|a0||a1||a2||a3||a4||a5||a7|xmm1

Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result byte i comes from byte i of xmm2. Result bytes 7 to 0: |a7|, unchanged (bit 6 of k1 is 0), |a5|, |a4|, |a3|, |a2|, |a1|, |a0|.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        zmm1.b[i] = abs(src2.sb[i])
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPABSB xmm, xmm/m128 VPABSB ymm, ymm/m256
xmm, ymmexplicitwrite
xmm/m128, ymm/m256explicitread
VPABSB xmm {k}{z}, xmm/m128 VPABSB ymm {k}{z}, ymm/m256 VPABSB zmm {k}{z}, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPABSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_abs_epi8 __m128i _mm_abs_epi8(__m128i __a)

VPABSB xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_abs_epi8 __m128i _mm_mask_abs_epi8(__m128i __W, __mmask16 __U, __m128i __A)

VPABSB xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_abs_epi8 __m128i _mm_maskz_abs_epi8(__mmask16 __U, __m128i __A)

VPABSB xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_abs_epi8 __m256i _mm256_abs_epi8(__m256i __a)

VPABSB ymm, ymm VEX.256 -mavx2

_mm256_mask_abs_epi8 __m256i _mm256_mask_abs_epi8(__m256i __W, __mmask32 __U, __m256i __A)

VPABSB ymm {k}, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_abs_epi8 __m256i _mm256_maskz_abs_epi8(__mmask32 __U, __m256i __A)

VPABSB ymm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_abs_epi8 __m512i _mm512_abs_epi8(__m512i __A)

VPABSB zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_abs_epi8 __m512i _mm512_mask_abs_epi8(__m512i __W, __mmask64 __U, __m512i __A)

VPABSB zmm {k}, zmm EVEX.512 -mavx512bw

_mm512_maskz_abs_epi8 __m512i _mm512_maskz_abs_epi8(__mmask64 __U, __m512i __A)

VPABSB zmm {k}{z}, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-177 (PABSB/PABSW/PABSD/PABSQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.