x86-64.net

Instruction

VPABSD

Computes the absolute value of packed signed doublewords.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPABSD replaces each doubleword with its absolute value. It is the VEX and EVEX form of SSSE3’s PABSD: VEX.128 needs AVX, VEX.256 AVX2, and the EVEX forms add masking, a broadcast source and the 512-bit width. VPABSB and VPABSW do the same for bytes and words, and AVX-512 added VPABSQ for quadwords.

The most negative value

-2147483648 has no positive counterpart in 32 bits, and VPABSD leaves it as it is: the cases recorded on Zen 5 turned 80000000h into 80000000h, FFFFFFFFh into 1 and 7FFFFFFFh into itself. Nothing saturates and no flag reports it. Read as unsigned, though, 80000000h is 2147483648, the correct magnitude, so storing the results into uint32_t gives the right answer for every input; only code that keeps treating them as signed sees a negative absolute value. C’s abs has the same hole, as undefined behaviour.

Without it

Before SSSE3 the usual sequence is a sign mask and two operations: shift a copy right arithmetically by 31 with PSRAD, giving 0 or -1, XOR it into the value and subtract it, which flips the bits and adds one exactly for negative elements. GCC 14 at -O2 emits that for the SSE2 baseline; with -msse4.1 or -march=x86-64-v3, GCC 14 and Clang 23 turn a[i] < 0 ? -a[i] : a[i] into PABSD or VPABSD, and the same applied to a[i] - b[i] into a subtraction and VPABSD.

For 64-bit elements AVX2 has no absolute value. With -march=x86-64-v3 GCC 14 builds the sign mask with VPCMPGTQ against zero and then XORs and subtracts, while Clang 23 subtracts from zero and picks the negated value by sign with VBLENDVPD; with -march=x86-64-v4 both use VPABSQ.

PSIGND and its VEX form are the related SSSE3 instruction that negates, keeps or zeroes each element by the sign of a second operand; it has no EVEX form. AMD’s Zen 5 guide lists VPABSD, VEX or EVEX, as one macro-op with a latency of 2 cycles on two of the four vector pipelines, where VPMAXSD takes one cycle on any of the four.

Forms

Every encoding of VPABSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPABSD xmm, m128 VPABSD_XMMdq_MEMdqVEX.128.66.0F38.WIG 1E /rAVX
VPABSD xmm, xmm VPABSD_XMMdq_XMMdqVEX.128.66.0F38.WIG 1E /rAVX
VPABSD ymm, m256 VPABSD_YMMqq_MEMqqVEX.256.66.0F38.WIG 1E /rAVX2
VPABSD ymm, ymm VPABSD_YMMqq_YMMqqVEX.256.66.0F38.WIG 1E /rAVX2
VPABSD zmm {k}{z}, zmm VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512EVEX.512.66.0F38.W0 1E /rAVX10.1 or AVX512F
VPABSD zmm {k}{z}, m512/m32bcst VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512EVEX.512.66.0F38.W0 1E /rAVX10.1 or AVX512F
VPABSD xmm {k}{z}, xmm VPABSD_XMMi32_MASKmskw_XMMi32_AVX512EVEX.128.66.0F38.W0 1E /rAVX10.1 or AVX512F + AVX512VL
VPABSD xmm {k}{z}, m128/m32bcst VPABSD_XMMi32_MASKmskw_MEMi32_AVX512EVEX.128.66.0F38.W0 1E /rAVX10.1 or AVX512F + AVX512VL
VPABSD ymm {k}{z}, ymm VPABSD_YMMi32_MASKmskw_YMMi32_AVX512EVEX.256.66.0F38.W0 1E /rAVX10.1 or AVX512F + AVX512VL
VPABSD ymm {k}{z}, m256/m32bcst VPABSD_YMMi32_MASKmskw_MEMi32_AVX512EVEX.256.66.0F38.W0 1E /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m128
xmm {k}{z}, m128/m32bcst		xmm, xmm
xmm {k}{z}, xmm		ymm, m256
ymm {k}{z}, m256/m32bcst		ymm, ymmzmm {k}{z}, zmmzmm {k}{z}, m512/m32bcstymm {k}{z}, ymm
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p011 / 1p08 / 1p01 / 0.5p01
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p011 / 1p09 / 1p01 / 0.5p01
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1
Zen 48 / 0.5FP0 FP1 FP2 FP32 / 11FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP11 / 0.52FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.253FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1811; AMD 58455, row 1223).
  2. Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1815; AMD 58455, row 372).
  3. Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1814; AMD 58455, row 372).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.
VPABSD: element by elementResult doubleword i comes from doubleword i of xmm2. Result doublewords 3 to 0: |a3|, unchanged (bit 2 of k1 is 0), |a1|, |a0|.0123xmm2or m128a1110k1|a0||a1||a3|xmm1

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of the last source.

Result doubleword i comes from doubleword i of xmm2. Result doublewords 3 to 0: |a3|, unchanged (bit 2 of k1 is 0), |a1|, |a0|.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = abs(src2.sd[i])
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPABSD xmm, xmm/m128 VPABSD ymm, ymm/m256
xmm, ymmexplicitwrite
xmm/m128, ymm/m256explicitread
VPABSD xmm {k}{z}, xmm/m128/m32bcst VPABSD ymm {k}{z}, ymm/m256/m32bcst VPABSD zmm {k}{z}, zmm/m512/m32bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPABSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_abs_epi32 __m128i _mm_abs_epi32(__m128i __a)

VPABSD xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_abs_epi32 __m128i _mm_mask_abs_epi32(__m128i __W, __mmask8 __U, __m128i __A)

VPABSD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_abs_epi32 __m128i _mm_maskz_abs_epi32(__mmask8 __U, __m128i __A)

VPABSD xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_abs_epi32 __m256i _mm256_abs_epi32(__m256i __a)

VPABSD ymm, ymm VEX.256 -mavx2

_mm256_mask_abs_epi32 __m256i _mm256_mask_abs_epi32(__m256i __W, __mmask8 __U, __m256i __A)

VPABSD ymm {k}, ymm EVEX.256 -mavx512vl

_mm256_maskz_abs_epi32 __m256i _mm256_maskz_abs_epi32(__mmask8 __U, __m256i __A)

VPABSD ymm {k}{z}, ymm EVEX.256 -mavx512vl

_mm512_abs_epi32 __m512i _mm512_abs_epi32(__m512i __A)

VPABSD zmm, zmm EVEX.512 -mavx512f

_mm512_mask_abs_epi32 __m512i _mm512_mask_abs_epi32(__m512i __W, __mmask16 __U, __m512i __A)

VPABSD zmm {k}, zmm EVEX.512 -mavx512f

_mm512_maskz_abs_epi32 __m512i _mm512_maskz_abs_epi32(__mmask16 __U, __m512i __A)

VPABSD zmm {k}{z}, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-177 (PABSB/PABSW/PABSD/PABSQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.