Instruction
VPABSQ
Computes the absolute value of packed signed quadwords.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VPABSQ replaces each quadword with its absolute value. It is
AVX-512F’s quadword form of VPABSD, whose page covers
the most negative value and the sequences that AVX2 code uses instead,
since AVX2 has no absolute value of quadwords. VPABSQ exists in EVEX
encodings only, with masking, a broadcast source and the 512-bit width.
The cases recorded on Zen 5 show the same edge as for doublewords:
8000000000000000h stayed 8000000000000000h, from a register and from a
broadcast, while FFFFFFFFFFFFFFFFh became 1 and 7FFFFFFFFFFFFFFFh
stayed itself. Taken as uint64_t, every result is the right
magnitude.
In compiled code
llabs(a[i] - b[i]) over int64_t arrays becomes a
VPSUBQ and VPABSQ with GCC 14 and Clang 23 at -O2 and
-march=x86-64-v4, and with a sum around it, the distance between two
vectors, a VPADDQ into an accumulator as well. The difference may
overflow there, as it may in the C source.
When the input is narrower, the compilers prefer the narrow
instruction: for llabs((int64_t)a[i]) with int32_t elements, both
take VPABSD of the doublewords and widen the results with
VPMOVZXDQ rather than sign-extending first and
using VPABSQ. Zero extension is right there, because the absolute
value of a 32-bit integer always fits 32 unsigned bits: 80000000h,
which VPABSD returns for -2147483648, becomes 2147483648.
For unsigned numbers there is no absolute value to take; the distance
a > b ? a - b : b - a is the larger minus the smaller, as the
VPMINUQ page shows.
AMD’s latency spreadsheet for Zen 5 lists VPABSQ as it lists VPABSD: one macro-op with a latency of 2 cycles on the pipes FP0 and FP3.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPABSQ zmm {k}{z}, zmm
VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 | EVEX.512.66.0F38.W1 1F /r | AVX10.1 or AVX512F |
VPABSQ zmm {k}{z}, m512/m64bcst
VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 | EVEX.512.66.0F38.W1 1F /r | AVX10.1 or AVX512F |
VPABSQ xmm {k}{z}, xmm
VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 | EVEX.128.66.0F38.W1 1F /r | AVX10.1 or AVX512F + AVX512VL |
VPABSQ xmm {k}{z}, m128/m64bcst
VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 | EVEX.128.66.0F38.W1 1F /r | AVX10.1 or AVX512F + AVX512VL |
VPABSQ ymm {k}{z}, ymm
VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 | EVEX.256.66.0F38.W1 1F /r | AVX10.1 or AVX512F + AVX512VL |
VPABSQ ymm {k}{z}, m256/m64bcst
VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 | EVEX.256.66.0F38.W1 1F /r | AVX10.1 or AVX512F + AVX512VL |
Latency and throughput
| Model | zmm {k}{z}, zmm | zmm {k}{z}, m512/m64bcst | xmm {k}{z}, xmm | xmm {k}{z}, m128/m64bcst | ymm {k}{z}, ymm | ymm {k}{z}, m256/m64bcst |
|---|---|---|---|---|---|---|
| Skylake-SP, Ice Lake | 1 / 1p0 | 8 / 1p0 | 1 / 0.5p01 | 7 / 0.5p01 | 1 / 0.5p01 | 8 / 0.5p01 |
| Sapphire Rapids | 1 / 1p0 | 9 / 1p0 | 1 / 0.5p01 | 8 / 0.5p01 | 1 / 0.5p01 | 9 / 0.5p01 |
| Zen 4 | 1 / 0.51FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 2 / 12FP0 FP1 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.253FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 |
- Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1818; AMD 58455, row 374).
- Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1816; AMD 58455, row 374).
- Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1817; AMD 58455, row 374).
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every quadword works alike: 2, 4 and 8 quadwords in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m64bcst, one quadword from memory stands for every element of the last source.
Result quadword i comes from quadword i of xmm2. Result quadwords 1 to 0: |a1|, |a0|.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 64):
if k1[i]:
zmm1.q[i] = abs(src2.sq[i])
elif zeroing:
zmm1.q[i] = 0
# else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 6 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPABSQ xmm {k}{z}, xmm/m128/m64bcst VPABSQ ymm {k}{z}, ymm/m256/m64bcst VPABSQ zmm {k}{z}, zmm/m512/m64bcst | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking
- Memory forms
- embedded broadcast (tuple Full); memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPABSQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_abs_epi64
__m128i _mm_abs_epi64(__m128i __A) |
|
_mm_mask_abs_epi64
__m128i _mm_mask_abs_epi64(__m128i __W, __mmask8 __U, __m128i __A) |
|
_mm_maskz_abs_epi64
__m128i _mm_maskz_abs_epi64(__mmask8 __U, __m128i __A) |
|
_mm256_abs_epi64
__m256i _mm256_abs_epi64(__m256i __A) |
|
_mm256_mask_abs_epi64
__m256i _mm256_mask_abs_epi64(__m256i __W, __mmask8 __U, __m256i __A) |
|
_mm256_maskz_abs_epi64
__m256i _mm256_maskz_abs_epi64(__mmask8 __U, __m256i __A) |
|
_mm512_abs_epi64
__m512i _mm512_abs_epi64(__m512i __A) |
|
_mm512_mask_abs_epi64
__m512i _mm512_mask_abs_epi64(__m512i __W, __mmask8 __U, __m512i __A) |
|
_mm512_maskz_abs_epi64
__m512i _mm512_maskz_abs_epi64(__mmask8 __U, __m512i __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512F_512 | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6 |
AVX512F_128 | AVX10.1 or AVX512F + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6 |
AVX512F_256 | Same as AVX512F_128 | Same as AVX512F_128 |
More AVX10.1 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-177 (PABSB/
PABSW/ PABSD/ PABSQ) - Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.