x86-64.net

Instruction

VPABSW

Computes the absolute value of packed signed words.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPABSW replaces each signed word with its absolute value: the VEX and EVEX form of PABSW, whose page covers the operation, with the encodings of VPABSB: AVX for VEX.128, AVX2 for VEX.256, and AVX512BW for the EVEX forms, with masking and the 512-bit width but no broadcast. On Zen 5, the recorded vpabsw ymm7, ymmword ptr [mem] turned FFFFh into 0001h and kept 7FFFh and 8000h, across all sixteen words, and vpabsw xmm7{k4}{z}, xmmword ptr [mem] zeroed the three words k4 leaves out.

Absolute differences

Intel’s optimization manual computes the absolute difference of signed words as a PSUBW and a PABSW (Section 6.6.2, Example 6-19). That pair is exact only while the difference fits in 16 bits: 7FFFh minus 8000h wraps to FFFFh, whose absolute value is 1. For C’s abs(b[i] - c[i]) over int16_t, where the subtraction happens in int, our builds at -O2 with -march=x86-64-v3 and -march=x86-64-v4 avoid it:

  • stored into uint16_t, GCC 14 widens both inputs to doublewords with VPMOVSXWD, subtracts and takes VPABSD, then narrows; Clang 23 subtracts the signed minimum from the maximum, VPMAXSW, VPMINSW and VPSUBW, a result that is right when read as unsigned;
  • for bytes, abs(b[i] - c[i]) over uint8_t widens to words in GCC, where VPSUBW cannot overflow, and takes VPABSW before narrowing back.

The plain absolute value of int16_t elements is one VPABSW in both compilers, from memory. AMD’s latency spreadsheet for Zen 5 gives VPABSW, VEX or EVEX, a latency of two cycles and two per cycle on pipes FP0 and FP3.

Forms

Every encoding of VPABSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPABSW xmm, m128 VPABSW_XMMdq_MEMdqVEX.128.66.0F38.WIG 1D /rAVX
VPABSW xmm, xmm VPABSW_XMMdq_XMMdqVEX.128.66.0F38.WIG 1D /rAVX
VPABSW ymm, m256 VPABSW_YMMqq_MEMqqVEX.256.66.0F38.WIG 1D /rAVX2
VPABSW ymm, ymm VPABSW_YMMqq_YMMqqVEX.256.66.0F38.WIG 1D /rAVX2
VPABSW xmm {k}{z}, xmm VPABSW_XMMi16_MASKmskw_XMMi16_AVX512EVEX.128.66.0F38.WIG 1D /rAVX10.1 or AVX512BW + AVX512VL
VPABSW xmm {k}{z}, m128 VPABSW_XMMi16_MASKmskw_MEMi16_AVX512EVEX.128.66.0F38.WIG 1D /rAVX10.1 or AVX512BW + AVX512VL
VPABSW ymm {k}{z}, ymm VPABSW_YMMi16_MASKmskw_YMMi16_AVX512EVEX.256.66.0F38.WIG 1D /rAVX10.1 or AVX512BW + AVX512VL
VPABSW ymm {k}{z}, m256 VPABSW_YMMi16_MASKmskw_MEMi16_AVX512EVEX.256.66.0F38.WIG 1D /rAVX10.1 or AVX512BW + AVX512VL
VPABSW zmm {k}{z}, zmm VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512EVEX.512.66.0F38.WIG 1D /rAVX10.1 or AVX512BW
VPABSW zmm {k}{z}, m512 VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512EVEX.512.66.0F38.WIG 1D /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m128
xmm {k}{z}, m128no mask		xmm, xmm
xmm {k}{z}, xmmno mask		ymm, m256
ymm {k}{z}, m256no mask		ymm, ymmxmm {k}{z}, xmmwith a mask, zeroingxmm {k}{z}, m128with a mask, zeroingymm {k}{z}, ymmno maskymm {k}{z}, ymmwith a mask, zeroingymm {k}{z}, m256with a mask, zeroingzmm {k}{z}, zmmno maskzmm {k}{z}, zmmwith a mask, zeroingzmm {k}{z}, m512no maskzmm {k}{z}, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p011 / 0.5p017 / 0.5p011 / 0.5p011 / 0.5p018 / 0.5p011 / 1p01 / 1p08 / 1p08 / 1p0
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p013 / 0.5p0111 / 0.5p011 / 0.5p013 / 0.5p0111 / 0.5p011 / 1p03 / 1p09 / 1p011 / 1p0
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1
Zen 48 / 0.5FP0 FP1 FP2 FP32 / 11FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP12 / 12FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.253FP0 FP1 FP2 FP31 / 0.253FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.54FP0 FP1 FP2 FP31 / 0.54FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1819; AMD 58455, row 1224).
  2. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1820; AMD 58455, row 373).
  3. Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1822; AMD 58455, row 373).
  4. Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1823; AMD 58455, row 373).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.
VPABSW: element by elementResult word i comes from word i of xmm2. Result words 7 to 0: |a7|, unchanged (bit 6 of k1 is 0), |a5|, |a4|, |a3|, |a2|, |a1|, |a0|.01234567xmm2or m128a11111110k1|a0||a1||a2||a3||a4||a5||a7|xmm1

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result word i comes from word i of xmm2. Result words 7 to 0: |a7|, unchanged (bit 6 of k1 is 0), |a5|, |a4|, |a3|, |a2|, |a1|, |a0|.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        zmm1.w[i] = abs(src2.sw[i])
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPABSW xmm, xmm/m128 VPABSW ymm, ymm/m256
xmm, ymmexplicitwrite
xmm/m128, ymm/m256explicitread
VPABSW xmm {k}{z}, xmm/m128 VPABSW ymm {k}{z}, ymm/m256 VPABSW zmm {k}{z}, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPABSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_abs_epi16 __m128i _mm_abs_epi16(__m128i __a)

VPABSW xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_abs_epi16 __m128i _mm_mask_abs_epi16(__m128i __W, __mmask8 __U, __m128i __A)

VPABSW xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_abs_epi16 __m128i _mm_maskz_abs_epi16(__mmask8 __U, __m128i __A)

VPABSW xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_abs_epi16 __m256i _mm256_abs_epi16(__m256i __a)

VPABSW ymm, ymm VEX.256 -mavx2

_mm256_mask_abs_epi16 __m256i _mm256_mask_abs_epi16(__m256i __W, __mmask16 __U, __m256i __A)

VPABSW ymm {k}, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_abs_epi16 __m256i _mm256_maskz_abs_epi16(__mmask16 __U, __m256i __A)

VPABSW ymm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_abs_epi16 __m512i _mm512_abs_epi16(__m512i __A)

VPABSW zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_abs_epi16 __m512i _mm512_mask_abs_epi16(__m512i __W, __mmask32 __U, __m512i __A)

VPABSW zmm {k}, zmm EVEX.512 -mavx512bw

_mm512_maskz_abs_epi16 __m512i _mm512_maskz_abs_epi16(__mmask32 __U, __m512i __A)

VPABSW zmm {k}{z}, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-177 (PABSB/PABSW/PABSD/PABSQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  9. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.