x86-64.net

Instruction

VPACKSSDW

Narrows signed doublewords from two sources to words with signed saturation.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPACKSSDW narrows doublewords to words with signed saturation: each doubleword, read as signed, is clamped to -32768..32767, and the words of the first source come before those of the second. It is the VEX and EVEX form of SSE2’s PACKSSDW and works like VPACKUSWB, whose page covers the packing and its lanes: above 128 bits, each lane packs four doublewords of the first source, then four of the second. On Zen 5, vpackssdw ymm1, ymm2, ymm3 turned 00008001h and 0000FFFFh into 7FFFh, where truncation would give 8001h and FFFFh, and FFFF7FFFh into 8000h, and filled words 8 to 11 from the upper lane of YMM2, not from YMM3.

A broadcast doubleword

The EVEX forms need AVX512BW (or AVX10.1) and take a write mask per result word. Unlike the byte and word packs, the sources here are doublewords, so the second one may be a single doubleword broadcast from memory. With -march=x86-64-v4, Clang 23 compiles _mm512_maskz_packs_epi32(m, a, _mm512_set1_epi32(*p)) to vpackssdw zmm0{k1}{z}, zmm0, dword ptr [rsi]{1to16}; GCC 14 first loads the value with VPBROADCASTD.

In compiled code

To clamp int32_t to int16_t, written as x < -32768 ? -32768 : x > 32767 ? 32767 : x, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 take different paths:

  • Clang lets the instruction clamp, and avoids the lane order by packing 128-bit halves, vpackssdw xmm0, xmm0, [mem].
  • GCC clamps with VPMINSD and VPMAXSD, clears the high halves with VPAND, packs with the unsigned VPACKUSDW and repairs the order with VPERMQ, the same steps as for a plain truncation (int16_t)b[i], where the AND keeps the packs from saturating.

With -march=x86-64-v4, neither packs in these loops: Clang stores the clamp with VPMOVSDW, which saturates the same way from one source and keeps the order, and the truncation with VPMOVDW; GCC clamps as before and gathers the words with VPERMT2W.

AMD’s latency spreadsheet for Zen 5 gives VPACKSSDW 2 cycles and two per cycle on pipes 1 and 2, as for VPACKUSWB. Zen 5’s 10 recorded cases cover every form, merging, zeroing and with a broadcast doubleword.

Forms

Every encoding of VPACKSSDW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPACKSSDW xmm, xmm, m128 VPACKSSDW_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 6B /rAVX
VPACKSSDW xmm, xmm, xmm VPACKSSDW_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 6B /rAVX
VPACKSSDW ymm, ymm, m256 VPACKSSDW_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 6B /rAVX2
VPACKSSDW ymm, ymm, ymm VPACKSSDW_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 6B /rAVX2
VPACKSSDW xmm {k}{z}, xmm, xmm VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512EVEX.128.66.0F.W0 6B /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSDW xmm {k}{z}, xmm, m128/m32bcst VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512EVEX.128.66.0F.W0 6B /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSDW ymm {k}{z}, ymm, ymm VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512EVEX.256.66.0F.W0 6B /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSDW ymm {k}{z}, ymm, m256/m32bcst VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512EVEX.256.66.0F.W0 6B /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSDW zmm {k}{z}, zmm, zmm VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512EVEX.512.66.0F.W0 6B /rAVX10.1 or AVX512BW
VPACKSSDW zmm {k}{z}, zmm, m512/m32bcst VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512EVEX.512.66.0F.W0 6B /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m32bcstno mask, broadcast		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256/m32bcstno mask, broadcast		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128/m32bcstwith a mask, zeroingymm {k}{z}, ymm, m256/m32bcstwith a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512/m32bcstno mask, broadcastzmm {k}{z}, zmm, m512/m32bcstwith a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p51 / 1p58 / 1p58 / 1p5
Ice Lake10 / 1p53 / 1p511 / 1p53 / 1p53 / 1p510 / 1p511 / 1p53 / 1p53 / 1p511 / 1p511 / 1p5
Alder Lake10 / 1p53 / 1p511 / 1p53 / 1p5
Sapphire Rapids10 / 1p53 / 1p511 / 1p53 / 1p55 / 1p513 / 1p513 / 1p53 / 1p55 / 1p511 / 1p513 / 1p5
Lunar Lake9 / 2V2 V33 / 1.5V2 V310 / 2.33V2 V33 / 1.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP22 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP1 FP22 / 1FP1 FP28 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Pack: the doublewords of both sources are narrowed to words with saturation; those of xmm2 fill the low half, those of xmm3 the high half.
VPACKSSDW: two sources narrowed into oneResult words 7 to 0: b3, unchanged (bit 6 of k1 is 0), b1, b0, a3, a2, a1, a0.0123xmm2a11111110k1a0a1a2a3b0b1b3xmm10123xmm3or m128b

The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of xmm3.

Result words 7 to 0: b3, unchanged (bit 6 of k1 is 0), b1, b0, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    j = i // 8 * 4 + i % 4
    if k1[i]:  # 1 without a write mask
        if i % 8 < 4:
            zmm1.w[i] = ssat(zmm2.sd[j], 16)
        else:
            zmm1.w[i] = ssat(src3.sd[j], 16)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPACKSSDW xmm, xmm, xmm/m128 VPACKSSDW ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPACKSSDW xmm {k}{z}, xmm, xmm/m128/m32bcst VPACKSSDW ymm {k}{z}, ymm, ymm/m256/m32bcst VPACKSSDW zmm {k}{z}, zmm, zmm/m512/m32bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPACKSSDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_packs_epi32 __m128i _mm_packs_epi32(__m128i __a, __m128i __b)

VPACKSSDW xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_packs_epi32 __m128i _mm_mask_packs_epi32(__m128i __W, __mmask8 __M, __m128i __A, __m128i __B)

VPACKSSDW xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_packs_epi32 __m128i _mm_maskz_packs_epi32(__mmask8 __M, __m128i __A, __m128i __B)

VPACKSSDW xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_packs_epi32 __m256i _mm256_packs_epi32(__m256i __a, __m256i __b)

VPACKSSDW ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_packs_epi32 __m256i _mm256_mask_packs_epi32(__m256i __W, __mmask16 __M, __m256i __A, __m256i __B)

VPACKSSDW ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_packs_epi32 __m256i _mm256_maskz_packs_epi32(__mmask16 __M, __m256i __A, __m256i __B)

VPACKSSDW ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_packs_epi32 __m512i _mm512_packs_epi32(__m512i __A, __m512i __B)

VPACKSSDW zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_packs_epi32 __m512i _mm512_mask_packs_epi32(__m512i __W, __mmask32 __M, __m512i __A, __m512i __B)

VPACKSSDW zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_packs_epi32 __m512i _mm512_maskz_packs_epi32(__mmask32 __M, __m512i __A, __m512i __B)

VPACKSSDW zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-183 (PACKSSWB/PACKSSDW)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.