x86-64.net

Instruction

VPACKSSWB

Narrows signed words from two sources to bytes with signed saturation.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPACKSSWB is the VEX and EVEX form of PACKSSWB, whose page covers the clamp of signed words to -128..127. The newer encodings add a separate destination, a memory operand at any alignment, clearing above the vector width, the 256-bit form (AVX2) and the EVEX forms, which need AVX512BW (or AVX10.1) and take a write mask per byte. Above 128 bits, each lane packs on its own, as VPACKUSWB explains: on Zen 5, vpacksswb ymm7, ymm11, ymmword ptr [mem] filled bytes 16 to 23 of the result from words 8 to 15 of YMM11, not from the memory operand, turning 0080h and 0081h into 7Fh and FF80h and FF7Fh into 80h.

No word broadcast

The sources are words, and embedded broadcast needs 32-bit or 64-bit elements (Intel’s optimization manual, Section 17.9.1). So for _mm512_maskz_packs_epi16(m, a, _mm512_set1_epi16(*p)), GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 load the word with VPBROADCASTW first, where the doubleword packs can fold a {1to16} operand.

Packing compare results

Word compares give 0000h or FFFFh, and signed saturation keeps them as 00h and FFh. For d[i] = a[i] < b[i] ? -1 : 0 with int16_t sources and int8_t results, in our builds at -O2 with -march=x86-64-v3, Clang compares 16 words with VPCMPGTW, moves the upper half down with VEXTRACTI128 and packs the two halves with the xmm form, so the lanes never get in the way. GCC reduces the compare results to 0 or 1, packs two registers with VPACKUSWB, repairs the order with VPERMQ and negates with VPSUBB. With -march=x86-64-v4 neither packs: Clang compares into a mask register and expands it with VPMOVM2B, and GCC narrows with VPMOVWB.

AMD’s latency spreadsheet for Zen 5 gives VPACKSSWB 2 cycles and two per cycle at every width. Zen 5’s 10 recorded cases cover every form, merging and zeroing included.

Forms

Every encoding of VPACKSSWB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPACKSSWB xmm, xmm, m128 VPACKSSWB_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 63 /rAVX
VPACKSSWB xmm, xmm, xmm VPACKSSWB_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 63 /rAVX
VPACKSSWB ymm, ymm, m256 VPACKSSWB_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 63 /rAVX2
VPACKSSWB ymm, ymm, ymm VPACKSSWB_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 63 /rAVX2
VPACKSSWB xmm {k}{z}, xmm, xmm VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512EVEX.128.66.0F.WIG 63 /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSWB xmm {k}{z}, xmm, m128 VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512EVEX.128.66.0F.WIG 63 /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSWB ymm {k}{z}, ymm, ymm VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512EVEX.256.66.0F.WIG 63 /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSWB ymm {k}{z}, ymm, m256 VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512EVEX.256.66.0F.WIG 63 /rAVX10.1 or AVX512BW + AVX512VL
VPACKSSWB zmm {k}{z}, zmm, zmm VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512EVEX.512.66.0F.WIG 63 /rAVX10.1 or AVX512BW
VPACKSSWB zmm {k}{z}, zmm, m512 VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512EVEX.512.66.0F.WIG 63 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p51 / 1p58 / 1p58 / 1p5
Ice Lake10 / 1p53 / 1p511 / 1p53 / 1p53 / 1p510 / 1p511 / 1p53 / 1p53 / 1p511 / 1p511 / 1p5
Alder Lake10 / 1p53 / 1p511 / 1p53 / 1p5
Sapphire Rapids10 / 1p53 / 1p511 / 1p53 / 1p55 / 1p513 / 1p513 / 1p53 / 1p55 / 1p511 / 1p513 / 1p5
Lunar Lake9 / 2V2 V33 / 1.5V2 V310 / 2.33V2 V33 / 1.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP22 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP1 FP22 / 1FP1 FP28 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Pack: the words of both sources are narrowed to bytes with saturation; those of xmm2 fill the low half, those of xmm3 the high half.
VPACKSSWB: two sources narrowed into oneResult bytes 15 to 0: b7, unchanged (bit 14 of k1 is 0), b5, b4, b3, b2, b1, b0, a7, a6, a5, a4, a3, a2, a1, a0.01234567xmm2a1111111111111110k1a0a1a2a3a4a5a6a7b0b1b2b3b4b5b7xmm101234567xmm3or m128b

The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result bytes 15 to 0: b7, unchanged (bit 14 of k1 is 0), b5, b4, b3, b2, b1, b0, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    j = i // 16 * 8 + i % 8
    if k1[i]:  # 1 without a write mask
        if i % 16 < 8:
            zmm1.b[i] = ssat(zmm2.sw[j], 8)
        else:
            zmm1.b[i] = ssat(src3.sw[j], 8)
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPACKSSWB xmm, xmm, xmm/m128 VPACKSSWB ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPACKSSWB xmm {k}{z}, xmm, xmm/m128 VPACKSSWB ymm {k}{z}, ymm, ymm/m256 VPACKSSWB zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPACKSSWB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_packs_epi16 __m128i _mm_packs_epi16(__m128i __a, __m128i __b)

VPACKSSWB xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_packs_epi16 __m128i _mm_mask_packs_epi16(__m128i __W, __mmask16 __M, __m128i __A, __m128i __B)

VPACKSSWB xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_packs_epi16 __m128i _mm_maskz_packs_epi16(__mmask16 __M, __m128i __A, __m128i __B)

VPACKSSWB xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_packs_epi16 __m256i _mm256_packs_epi16(__m256i __a, __m256i __b)

VPACKSSWB ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_packs_epi16 __m256i _mm256_mask_packs_epi16(__m256i __W, __mmask32 __M, __m256i __A, __m256i __B)

VPACKSSWB ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_packs_epi16 __m256i _mm256_maskz_packs_epi16(__mmask32 __M, __m256i __A, __m256i __B)

VPACKSSWB ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_packs_epi16 __m512i _mm512_packs_epi16(__m512i __A, __m512i __B)

VPACKSSWB zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_packs_epi16 __m512i _mm512_mask_packs_epi16(__m512i __W, __mmask64 __M, __m512i __A, __m512i __B)

VPACKSSWB zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_packs_epi16 __m512i _mm512_maskz_packs_epi16(__mmask64 __M, __m512i __A, __m512i __B)

VPACKSSWB zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-183 (PACKSSWB/PACKSSDW)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  9. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.