VPACKUSDW

VPACKUSDW is the VEX and EVEX form of SSE4.1’s PACKUSDW, whose page covers the clamp of signed doublewords to 0..65535 and why unsigned input has to be clamped first. The newer encodings add a separate destination, a memory operand at any alignment, clearing above the vector width, the 256-bit form (AVX2) and the EVEX forms, which need AVX512BW (or AVX10.1) and take a write mask per word. Above 128 bits each lane packs on its own, as VPACKSSDW explains: on Zen 5, vpackusdw ymm8, ymm15, ymmword ptr [mem] filled words 8 to 11 from doublewords 4 to 7 of YMM15, turning 7FFFFFFFh into FFFFh and 00000055h into 0055h.

A broadcast doubleword#

The sources are doublewords, so the second may be one doubleword from memory repeated, {1to4} to {1to16}. The recorded vpackusdw zmm17{k7}, zmm30, dword bcst [mem], with 00008001h in memory, wrote 8001h into every selected word from that source, and turned FFFFFFFFh from ZMM30 into 0 and 00007FFFh into 7FFFh. For _mm512_maskz_packus_epi32 with _mm512_set1_epi32(*p), Clang 23 folds the broadcast into the operand, while GCC 14 first loads it with VPBROADCASTD.

In compiled code#

To clamp int32_t to 0..65535 into uint16_t, in our builds at -O2 with -march=x86-64-v3, Clang packs 128-bit halves with the xmm form, which clamps by itself and keeps the order; GCC clamps with VPMINSD and VPMAXSD, masks with VPAND, packs ymm registers and repairs the lane order with VPERMQ. With -march=x86-64-v4 neither packs. Clang raises negative values to 0 with VPMAXSD and stores with VPMOVUSDW, whose saturation reads doublewords as unsigned and would turn them into FFFFh; GCC clamps as before and gathers the words with VPERMT2W.

AMD’s latency spreadsheet for Zen 5 gives VPACKUSDW 2 cycles and two per cycle at every width. Zen 5’s 10 recorded cases cover every form, merging, zeroing and with a broadcast doubleword.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    j = i // 8 * 4 + i % 4
    if k1[i]:  # 1 without a write mask
        if i % 8 < 4:
            zmm1.w[i] = usat(zmm2.sd[j], 16)
        else:
            zmm1.w[i] = usat(src3.sd[j], 16)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPACKUSDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 253 AVX instructions

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW

All 686 AVX10.1 instructions