x86-64.net

Instruction

VPACKUSWB

Narrows signed words from two sources to bytes with unsigned saturation.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPACKUSWB is PACKUSWB in VEX and EVEX encodings: it reads words as signed numbers, clamps each to 0..255 and packs the bytes of both sources into one register. The PACKUSWB page covers the clamp, the signed reading that turns 40000 into 00h, and its use after widened arithmetic. On Zen 5, vpackuswb ymm8, ymm15, ymm0 turned 8000h and FF80h into 00h and 7FFFh and 0100h into FFh.

Lane by lane

Above 128 bits, each 128-bit lane packs on its own: eight bytes from the lane of the first source, then eight from the same lane of the second. In the case above, whose sources held the same 32 bytes, bytes 16 to 23 of the result were words 8 to 15 clamped, from the upper lane, not the second source’s words 0 to 7. Data that fills whole registers comes out with its middle quarters swapped.

The PACKUSWB page shows GCC repairing the order with VPERMQ when compiling with -mavx2. At -O2 with -march=x86-64-v3, GCC 14 does the same for clamping int16_t to uint8_t, after VPMINSW, VPMAXSW and a VPAND that the clamp makes redundant. Clang 23 avoids the repair: it packs 128-bit halves, vpackuswb xmm0, xmm0, [mem], and lets the instruction do the whole clamp.

AVX-512

The EVEX forms need AVX512BW (or AVX10.1) and add a write mask per result byte. With -march=x86-64-v4, though, neither compiler packs in loops: the down-conversions VPMOVWB, which truncates, and VPMOVUSWB, which saturates words read as unsigned, take one source and keep the elements in order. GCC clamps with VPMINSW and VPMAXSW and narrows with VPMOVWB; Clang clamps at zero with VPMAXSW and stores with VPMOVUSWB. VPACKUSWB remains for the intrinsics, _mm512_maskz_packus_epi16 becoming vpackuswb zmm0{k1}{z}, zmm0, zmm1 in both.

AMD’s latency spreadsheet for Zen 5 gives VPACKUSWB 2 cycles and two per cycle on pipes 1 and 2, and VPMOVWB from zmm to ymm 4 cycles. Zen 5’s 10 recorded cases cover every form, merging and zeroing included.

Forms

Every encoding of VPACKUSWB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPACKUSWB xmm, xmm, m128 VPACKUSWB_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 67 /rAVX
VPACKUSWB xmm, xmm, xmm VPACKUSWB_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 67 /rAVX
VPACKUSWB ymm, ymm, m256 VPACKUSWB_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 67 /rAVX2
VPACKUSWB ymm, ymm, ymm VPACKUSWB_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 67 /rAVX2
VPACKUSWB xmm {k}{z}, xmm, xmm VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512EVEX.128.66.0F.WIG 67 /rAVX10.1 or AVX512BW + AVX512VL
VPACKUSWB xmm {k}{z}, xmm, m128 VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512EVEX.128.66.0F.WIG 67 /rAVX10.1 or AVX512BW + AVX512VL
VPACKUSWB ymm {k}{z}, ymm, ymm VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512EVEX.256.66.0F.WIG 67 /rAVX10.1 or AVX512BW + AVX512VL
VPACKUSWB ymm {k}{z}, ymm, m256 VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512EVEX.256.66.0F.WIG 67 /rAVX10.1 or AVX512BW + AVX512VL
VPACKUSWB zmm {k}{z}, zmm, zmm VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512EVEX.512.66.0F.WIG 67 /rAVX10.1 or AVX512BW
VPACKUSWB zmm {k}{z}, zmm, m512 VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512EVEX.512.66.0F.WIG 67 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p51 / 1p58 / 1p58 / 1p5
Ice Lake10 / 1p53 / 1p511 / 1p53 / 1p53 / 1p510 / 1p511 / 1p53 / 1p53 / 1p511 / 1p511 / 1p5
Alder Lake10 / 1p53 / 1p511 / 1p53 / 1p5
Sapphire Rapids10 / 1p53 / 1p511 / 1p53 / 1p55 / 1p513 / 1p513 / 1p53 / 1p55 / 1p511 / 1p513 / 1p5
Lunar Lake9 / 2V2 V33 / 1.5V2 V310 / 2.33V2 V33 / 1.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP22 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP1 FP22 / 1FP1 FP28 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Pack: the words of both sources are narrowed to bytes with saturation; those of xmm2 fill the low half, those of xmm3 the high half.
VPACKUSWB: two sources narrowed into oneResult bytes 15 to 0: b7, unchanged (bit 14 of k1 is 0), b5, b4, b3, b2, b1, b0, a7, a6, a5, a4, a3, a2, a1, a0.01234567xmm2a1111111111111110k1a0a1a2a3a4a5a6a7b0b1b2b3b4b5b7xmm101234567xmm3or m128b

The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result bytes 15 to 0: b7, unchanged (bit 14 of k1 is 0), b5, b4, b3, b2, b1, b0, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    j = i // 16 * 8 + i % 8
    if k1[i]:  # 1 without a write mask
        if i % 16 < 8:
            zmm1.b[i] = usat(zmm2.sw[j], 8)
        else:
            zmm1.b[i] = usat(src3.sw[j], 8)
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPACKUSWB xmm, xmm, xmm/m128 VPACKUSWB ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPACKUSWB xmm {k}{z}, xmm, xmm/m128 VPACKUSWB ymm {k}{z}, ymm, ymm/m256 VPACKUSWB zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPACKUSWB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_packus_epi16 __m128i _mm_packus_epi16(__m128i __a, __m128i __b)

VPACKUSWB xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_packus_epi16 __m128i _mm_mask_packus_epi16(__m128i __W, __mmask16 __M, __m128i __A, __m128i __B)

VPACKUSWB xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_packus_epi16 __m128i _mm_maskz_packus_epi16(__mmask16 __M, __m128i __A, __m128i __B)

VPACKUSWB xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_packus_epi16 __m256i _mm256_packus_epi16(__m256i __a, __m256i __b)

VPACKUSWB ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_packus_epi16 __m256i _mm256_mask_packus_epi16(__m256i __W, __mmask32 __M, __m256i __A, __m256i __B)

VPACKUSWB ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_packus_epi16 __m256i _mm256_maskz_packus_epi16(__mmask32 __M, __m256i __A, __m256i __B)

VPACKUSWB ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_packus_epi16 __m512i _mm512_packus_epi16(__m512i __A, __m512i __B)

VPACKUSWB zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_packus_epi16 __m512i _mm512_mask_packus_epi16(__m512i __W, __mmask64 __M, __m512i __A, __m512i __B)

VPACKUSWB zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_packus_epi16 __m512i _mm512_maskz_packus_epi16(__mmask64 __M, __m512i __A, __m512i __B)

VPACKUSWB zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-196 (PACKUSWB)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.