VPADDD

VPADDD is PADDD in VEX and EVEX encodings: it adds doublewords element by element and lets each sum wrap around, with no flags. The PADDD page covers the addition and its uses in compiled code, the vectorized sums and the all-ones constant among them. What the newer encodings add:

• A third operand. vpaddd ymm0, ymm1, [mem] keeps both sources, and the memory operand may sit at any address, so a load folds into the addition where legacy SSE needs a separate MOVDQU. GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 compile a[i] = b[i] + c[i] over 1,024 ints to one load, a VPADDD with a memory operand and a store per 32 bytes.
• Clearing above the width. The VEX.128 form clears bits 128 and up of the destination, as every VEX and EVEX form does above its width.
• Masks and a broadcast operand. The EVEX forms (AVX512F, or AVX10.1) add a write mask per doubleword, with merging or zeroing, and can read a single doubleword from memory and add it to every element ({1to16} for a zmm register).

Broadcasts in practice#

The compilers differ on the broadcast form. With -march=x86-64-v4, Clang 23 compiles _mm512_add_epi32(x, _mm512_set1_epi32(5)) to vpaddd zmm0, zmm0, dword ptr [rip + c]{1to16}, reading the constant from a 4-byte pool entry, and a masked add of *p to vpaddd zmm0{k1}, zmm1, dword ptr [rsi]{1to16}. GCC 14 first loads the value into a whole register with VPBROADCASTD and adds that. In a loop both broadcast once before it, so the difference matters in straight-line code.

That target also changes the width: GCC 14 vectorizes the loop above with zmm registers, 64 bytes at a time, while Clang 23 stays with ymm registers.

Zen 5’s 66 recorded cases cover every form: the VEX ones with a register or memory source, and the EVEX ones unmasked, merging, zeroing and with broadcast, including a destination that is also both sources (vpaddd zmm5{k3}, zmm5, zmm5).

In the optimization guide

What the optimization guide says about VPADDD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 2

• Vectors and floating point: A float addition or multiplication takes three cycles and an FMA five, each on two pipes, and VPADDD one cycle on any of three; AMD’s spreadsheet, LLVM’s model and Agner Fog agree.

Zen 3

• Vectors and floating point: LLVM’s model gives a float addition or multiplication three cycles and an FMA four, each on two pipes, and VPADDD one cycle on any of the four.

Zen 4

• Vectors and floating point: LLVM’s model gives VPADDD a latency of one cycle on any of the four pipes, and VFMADD231PS four cycles on pipe 0 or 1; the 512-bit forms keep their pipe for two cycles, so they finish half as many per cycle.

Zen 5

• Vectors and floating point: AMD’s latency spreadsheet gives VPADDD a latency of one cycle and a throughput of four per cycle, on any of the four vector pipes. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm2.d[i] + src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPADDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM

All 253 AVX instructions

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q

All 686 AVX10.1 instructions