x86-64.net

Instruction

VPADDQ

Adds packed quadwords, wrapping around on overflow.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPADDQ adds quadwords element by element and keeps the low 64 bits of each sum, wrapping around with no flags, the same for signed and unsigned numbers: on Zen 5, vpaddq xmm8, xmm15, [mem] turned 8000000000000000h plus itself into zero and 7FFFFFFFFFFFFFFFh plus itself into FFFFFFFFFFFFFFFEh. It is the VEX and EVEX form of SSE2’s PADDQ, and the encodings add what the VPADDD page lists for doublewords: a separate destination, a memory source at any address, 256 bits with AVX2 and 512 with AVX512F, and in EVEX a write mask per quadword and a broadcast quadword ({1to8} for zmm).

Where 64-bit sums come from

At -O2 with -march=x86-64-v3, GCC 14 and Clang 23 use VPADDQ for everything 64 bits wide:

  • int64_t and pointer arrays. a[i] = b[i] + c[i] over int64_t, and adding 16 to each pointer of an array of char *, are a VPADDQ per four elements.
  • Wider sums. Summing 1,024 ints into an int64_t sign-extends them first with VPMOVSXDQ and accumulates with VPADDQ, which a 32-bit sum would not need. Clang keeps four accumulators so that four additions can be in flight; GCC keeps one.
  • Products. AVX2 has no 64-bit multiply, and the low product of two quadwords is assembled from three VPMULUDQ with shifts and two VPADDQs.

AVX-512

With -march=x86-64-v4, GCC moves these loops to zmm registers while Clang stays with ymm. Both fold _mm512_set1_epi64(*p) into the addition as qword ptr [rdi]{1to8}. For a constant, Clang also broadcasts from an 8-byte pool entry, even on ymm registers ({1to4}), where GCC first moves the value into a register with VPBROADCASTQ.

AMD’s latency spreadsheet for Zen 5 gives VPADDQ one cycle and four per cycle, the same as VPADDD. Zen 5’s 10 recorded cases cover every form, among them a merging vpaddq zmm24{k6} and two with a broadcast quadword.

Forms

Every encoding of VPADDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPADDQ xmm, xmm, m128 VPADDQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG D4 /rAVX
VPADDQ xmm, xmm, xmm VPADDQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG D4 /rAVX
VPADDQ ymm, ymm, m256 VPADDQ_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG D4 /rAVX2
VPADDQ ymm, ymm, ymm VPADDQ_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG D4 /rAVX2
VPADDQ zmm {k}{z}, zmm, zmm VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512EVEX.512.66.0F.W1 D4 /rAVX10.1 or AVX512F
VPADDQ zmm {k}{z}, zmm, m512/m64bcst VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F.W1 D4 /rAVX10.1 or AVX512F
VPADDQ xmm {k}{z}, xmm, xmm VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F.W1 D4 /rAVX10.1 or AVX512F + AVX512VL
VPADDQ xmm {k}{z}, xmm, m128/m64bcst VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F.W1 D4 /rAVX10.1 or AVX512F + AVX512VL
VPADDQ ymm {k}{z}, ymm, ymm VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512EVEX.256.66.0F.W1 D4 /rAVX10.1 or AVX512F + AVX512VL
VPADDQ ymm {k}{z}, ymm, m256/m64bcst VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F.W1 D4 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m64bcst		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm		ymm, ymm, m256
ymm {k}{z}, ymm, m256/m64bcst		ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m64bcst
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p0151 / 0.33p0158 / 0.5p0151 / 0.33p015
Skylake-SP, Ice Lake7 / 0.5p0151 / 0.33p0158 / 0.5p0151 / 0.33p0151 / 0.33p0158 / 0.5p015
Alder Lake8 / 0.33p0151 / 0.33p0159 / 0.33p0151 / 0.33p015
Sapphire Rapids8 / 0.33p0151 / 0.33p0159 / 0.33p0151 / 0.33p0151 / 0.5p059 / 0.5p05
Lunar Lake7 / 2V0 V1 V2 V31 / 0.25V0 V1 V2 V38 / 2.33V0 V1 V2 V31 / 0.25V0 V1 V2 V3
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP3
Zen 48 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.
VPADDQ: element by elementResult quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: a1+b1, a0+b0.01xmm2a11k1a0+b0a1+b1xmm101xmm3or m128b

Every quadword works alike: 2, 4 and 8 quadwords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m64bcst, one quadword from memory stands for every element of the last source.

Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = zmm2.q[i] + src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPADDQ xmm, xmm, xmm/m128 VPADDQ ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPADDQ xmm {k}{z}, xmm, xmm/m128/m64bcst VPADDQ ymm {k}{z}, ymm, ymm/m256/m64bcst VPADDQ zmm {k}{z}, zmm, zmm/m512/m64bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPADDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_add_epi64 __m128i _mm_add_epi64(__m128i __a, __m128i __b)

VPADDQ xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_add_epi64 __m128i _mm_mask_add_epi64(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPADDQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_add_epi64 __m128i _mm_maskz_add_epi64(__mmask8 __U, __m128i __A, __m128i __B)

VPADDQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_add_epi64 __m256i _mm256_add_epi64(__m256i __a, __m256i __b)

VPADDQ ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_add_epi64 __m256i _mm256_mask_add_epi64(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B)

VPADDQ ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_add_epi64 __m256i _mm256_maskz_add_epi64(__mmask8 __U, __m256i __A, __m256i __B)

VPADDQ ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_add_epi64 __m512i _mm512_add_epi64(__m512i __A, __m512i __B)

VPADDQ zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_add_epi64 __m512i _mm512_mask_add_epi64(__m512i __W, __mmask8 __U, __m512i __A, __m512i __B)

VPADDQ zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_add_epi64 __m512i _mm512_maskz_add_epi64(__mmask8 __U, __m512i __A, __m512i __B)

VPADDQ zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-201 (PADDB/PADDW/PADDD/PADDQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.