VPADDSB

VPADDSB adds signed bytes and clamps each sum to the range -128 to 127 instead of letting it wrap: the VEX and EVEX form of SSE2’s PADDSB, whose page covers the clamp and how C code reaches it. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1, take a mask bit per byte and, like every byte and word form, cannot broadcast. Each form writes a separate destination, reads memory at any alignment and zeroes the register above the vector length; the bytes are independent, so the 128-bit lanes play no part. On Zen 5, vpaddsb xmm0, xmm13, xmm9 turned 7Fh plus 01h into 7Fh, 80h plus 80h into 80h and FFh plus 01h into 00h, and vpaddsb zmm5{k4}, zmm5, zmm5 doubled the bytes k4 selects, 7Fh and 80h staying as they were, and left the others alone.

In compiled code#

In our builds at -O2 over fixed-size int8_t arrays, for s = b[i] + c[i] clamped as on PADDSB’s page:

• Clang 23 emits one VPADDSB per 32 bytes with its second source in memory, at -march=x86-64-v3 and, still on ymm registers, at -v4. With if (m[i]) around the assignment at -v4, it tests the condition bytes into a mask with VPTESTMB, adds every byte and stores under the mask with VMOVDQU8.
• GCC 14 widens to words with VPMOVSXBW, adds with VPADDW, clamps with VPMAXSW and VPMINSW, and narrows back with VPACKUSWB and VPERMQ at -v3, or with VPMOVWB on zmm registers at -v4.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike two cycles and two per cycle, on pipes FP0 and FP3, where VPADDB takes one cycle at four per cycle. Intel’s optimization manual also puts the saturating additions of Golden Cove on its two vector adders and the wrapping ones on three vector ALUs (Table 2-4).

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        sa = zmm2.sb[i]
        sb = src3.sb[i]
        zmm1.b[i] = ssat(sa + sb, 8)
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPADDSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTB
• VPCMPGTD

All 253 AVX instructions

More AVX2 instructions

• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW

All 138 AVX2 instructions

More AVX10.1 instructions

• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ

All 686 AVX10.1 instructions