x86-64.net

Instruction

VPALIGNR

Concatenates two sources in each 128-bit lane and extracts 16 bytes starting at a byte offset given by an immediate.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPALIGNR is PALIGNR in VEX and EVEX encodings: it joins the first source above the second, shifts the pair right by the immediate number of bytes and keeps the low 16. The PALIGNR page covers the operand order and the uses, stitching unaligned data, sliding windows and byte rotation. The VEX.256 form of AVX2 and the EVEX forms of AVX512BW, with byte masking and 512 bits, do this in each 128-bit lane separately, with the same immediate: a 256-bit VPALIGNR is two 16-byte shifts side by side, not one 32-byte shift. Immediates from 16 up shift in zeros in every lane; the cases recorded on Zen 5 include 1Fh, which leaves only the top byte of the first source’s lane, moved to the bottom, and 8Fh, which gives zero.

A 32-byte window

The window that code usually wants, 32 bytes starting n bytes into the pair of registers a and b, therefore takes two instructions. For such a shuffle written with __builtin_shufflevector, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 first build the register that holds the upper half of a and the lower half of b with VPERM2I128, then take the window from it and a with vpalignr ymm0, ymm1, ymm0, n. When the shuffle is meant per lane, as _mm256_alignr_epi8(a, b, 5) is, one VPALIGNR does it.

Clang uses the same pair to vectorize a sum of neighbours such as d[i] = x[i] + x[i+1] + x[i+2], building the shifted vectors from registers it already loaded instead of loading again at unaligned addresses.

With AVX-512

AVX-512F added VALIGND and VALIGNQ, which shift across the whole register in units of doublewords or quadwords. For x86-64-v4 Clang takes a window that moves by 4 bytes, and the neighbour sum above, with one VALIGND, while GCC takes that window with VPERMI2D; a window that moves by a single byte still takes VPERM2I128 and VPALIGNR. With AVX512_VBMI, as for znver5, the byte window becomes one VPERMI2B in GCC or VPERMT2B in Clang.

AMD’s Zen 5 guide lists VPALIGNR as one macro-op with a latency of 2 cycles at every width; VPERM2I128 takes 3, and VALIGND 2, 4 and 5 cycles for xmm, ymm and zmm.

Forms

Every encoding of VPALIGNR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPALIGNR xmm, xmm, m128, imm8 VPALIGNR_XMMdq_XMMdq_MEMdq_IMMbVEX.128.66.0F3A.WIG 0F /r ibAVX
VPALIGNR xmm, xmm, xmm, imm8 VPALIGNR_XMMdq_XMMdq_XMMdq_IMMbVEX.128.66.0F3A.WIG 0F /r ibAVX
VPALIGNR ymm, ymm, m256, imm8 VPALIGNR_YMMqq_YMMqq_MEMqq_IMMbVEX.256.66.0F3A.WIG 0F /r ibAVX2
VPALIGNR ymm, ymm, ymm, imm8 VPALIGNR_YMMqq_YMMqq_YMMqq_IMMbVEX.256.66.0F3A.WIG 0F /r ibAVX2
VPALIGNR xmm {k}{z}, xmm, xmm, imm8 VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512EVEX.128.66.0F3A.WIG 0F /r ibAVX10.1 or AVX512BW + AVX512VL
VPALIGNR xmm {k}{z}, xmm, m128, imm8 VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512EVEX.128.66.0F3A.WIG 0F /r ibAVX10.1 or AVX512BW + AVX512VL
VPALIGNR ymm {k}{z}, ymm, ymm, imm8 VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512EVEX.256.66.0F3A.WIG 0F /r ibAVX10.1 or AVX512BW + AVX512VL
VPALIGNR ymm {k}{z}, ymm, m256, imm8 VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512EVEX.256.66.0F3A.WIG 0F /r ibAVX10.1 or AVX512BW + AVX512VL
VPALIGNR zmm {k}{z}, zmm, zmm, imm8 VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512EVEX.512.66.0F3A.WIG 0F /r ibAVX10.1 or AVX512BW
VPALIGNR zmm {k}{z}, zmm, m512, imm8 VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512EVEX.512.66.0F3A.WIG 0F /r ibAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128, imm8
xmm {k}{z}, xmm, m128, imm8no mask		xmm, xmm, xmm, imm8
xmm {k}{z}, xmm, xmm, imm8no mask
ymm {k}{z}, ymm, ymm, imm8no mask		ymm, ymm, m256, imm8
ymm {k}{z}, ymm, m256, imm8no mask		ymm, ymm, ymm, imm8xmm {k}{z}, xmm, xmm, imm8with a mask, zeroing
ymm {k}{z}, ymm, ymm, imm8with a mask, zeroing		xmm {k}{z}, xmm, m128, imm8with a mask, zeroingymm {k}{z}, ymm, m256, imm8with a mask, zeroingzmm {k}{z}, zmm, zmm, imm8no maskzmm {k}{z}, zmm, zmm, imm8with a mask, zeroingzmm {k}{z}, zmm, m512, imm8no maskzmm {k}{z}, zmm, m512, imm8with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP, Ice Lake7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p51 / 1p58 / 1p58 / 1p5
Alder Lake8 / 1p51 / 1p59 / 1p51 / 1p5
Sapphire Rapids8 / 1p51 / 1p59 / 1p51 / 1p53 / 1p511 / 1p511 / 1p51 / 1p53 / 1p59 / 1p511 / 1p5
Lunar Lake7 / 2V2 V31 / 0.33p1358 / 2.33V2 V31 / 0.33p135
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP22 / 0.5FP1 FP22 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP1 FP22 / 1FP1 FP28 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Align: xmm2 above xmm3 make one 32-byte value, shifted right by imm8 bytes; the low 16 are the result.
VPALIGNR with imm8 = 5With imm8 = 5, result bytes 15 to 0: a4, unchanged (bit 14 of k1 is 0), a2, a1, a0, b15, b14, b13, b12, b11, b10, b9, b8, b7, b6, b5.0123456789101112131415xmm2a1111111111111110k1b5b6b7b8b9b10b11b12b13b14b15a0a1a2a4xmm10123456789101112131415xmm3or m128b

Example: imm8 = 5. The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

With imm8 = 5, result bytes 15 to 0: a4, unchanged (bit 14 of k1 is 0), a2, a1, a0, b15, b14, b13, b12, b11, b10, b9, b8, b7, b6, b5.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    j = i % 16 + imm8  # byte j of the lane of zmm2:src3
    if j < 16:
        x = src3.b[i + imm8]
    elif j < 32:
        x = zmm2.b[i + imm8 - 16]
    else:
        x = 0
    if k1[i]:          # 1 without a write mask
        zmm1.b[i] = x
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPALIGNR xmm, xmm, xmm/m128, imm8 VPALIGNR ymm, ymm, ymm/m256, imm8
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
imm8explicitread
VPALIGNR xmm {k}{z}, xmm, xmm/m128, imm8 VPALIGNR ymm {k}{z}, ymm, ymm/m256, imm8 VPALIGNR zmm {k}{z}, zmm, zmm/m512, imm8
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPALIGNR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_alignr_epi32 __m128i _mm_alignr_epi32(__m128i A, __m128i B, const int imm)

VPALIGNR xmm, xmm, xmm, imm8 VEX.128 -mavx512vl

_mm_mask_alignr_epi8 __m128i _mm_mask_alignr_epi8(__m128i W, __mmask16 U, __m128i A, __m128i B, const int N)

VPALIGNR xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_alignr_epi8 __m128i _mm_maskz_alignr_epi8(__mmask16 U, __m128i A, __m128i B, const int N)

VPALIGNR xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm256_alignr_epi8 __m256i _mm256_alignr_epi8(__m256i a, __m256i b, const int n)

VPALIGNR ymm, ymm, ymm, imm8 VEX.256 -mavx2

_mm256_mask_alignr_epi8 __m256i _mm256_mask_alignr_epi8(__m256i W, __mmask32 U, __m256i A, __m256i B, const int N)

VPALIGNR ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_alignr_epi8 __m256i _mm256_maskz_alignr_epi8(__mmask32 U, __m256i A, __m256i B, const int N)

VPALIGNR ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm512_alignr_epi8 __m512i _mm512_alignr_epi8(__m512i A, __m512i B, const int N)

VPALIGNR zmm, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_alignr_epi8 __m512i _mm512_mask_alignr_epi8(__m512i W, __mmask64 U, __m512i A, __m512i B, const int N)

VPALIGNR zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_maskz_alignr_epi8 __m512i _mm512_maskz_alignr_epi8(__mmask64 U, __m512i A, __m512i B, const int N)

VPALIGNR zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-216 (PALIGNR)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.