VPAND instruction (AVX, AVX2)

VPAND computes the bitwise AND of two 128- or 256-bit values into a third register. It is the VEX form of PAND, with a memory operand at any address and, for the 128-bit form, the bits from 128 up cleared: on Zen 5, vpand xmm1, xmm2, xmm3 left all of ZMM1 zero. Element boundaries do not exist for it, so one instruction serves every integer type. There is no EVEX VPAND: VPANDD and VPANDQ are the same operation, named for the element size of their write mask. VPANDN inverts its first source before the AND.

Masks in integer code

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 use VPAND to keep some bits and clear the rest:

Selecting with a compare. b[i] > c[i] ? b[i] : 0 over ints is a VPCMPGTD, whose all-ones or zero elements then mask b with VPAND.
Truncating. Before VPACKUSWB narrows words to bytes, a VPAND with 00FFh per word removes the high bytes, so that its clamp changes nothing.

Which AND the compilers pick

AND gives the same bits under any name, and the compilers choose differently. GCC uses VPAND for integer data throughout. Clang uses VANDPS, of the same length in VEX, where the result is only moved, for _mm256_and_si256 and for a[i] = b[i] & c[i] or b[i] & 0xff, and VPAND when it feeds integer arithmetic, as in (b[i] & c[i]) + 1. With -march=x86-64-v4, GCC switches to the EVEX VPANDD on zmm registers in loops, and even compiles _mm256_and_si256 to VPANDQ on ymm registers, where Clang keeps the VEX forms.

AMD’s Zen 5 guide asks for instructions that match the type of the data they consume (Section 2.11.2), and its latency spreadsheet gives VPAND one cycle and four per cycle on any of the four vector pipes. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

Forms

Every encoding of VPAND that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPAND xmm, xmm, m128` VPAND_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F.WIG DB /r`	AVX
`VPAND xmm, xmm, xmm` VPAND_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F.WIG DB /r`	AVX
`VPAND ymm, ymm, m256` VPAND_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F.WIG DB /r`	AVX2
`VPAND ymm, ymm, ymm` VPAND_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F.WIG DB /r`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 2 and 4 quadwords in the xmm and ymm forms.

Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: a1&b1, a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    ymm1.q[i] = ymm2.q[i] & src3.q[i]
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPAND xmm, xmm, xmm/m128` `VPAND ymm, ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPAND, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_and_epi32` `__m128i _mm_and_epi32(__m128i __a, __m128i __b)`	`VPAND xmm, xmm, xmm` VEX.128 -mavx512vl
`_mm_and_epi64` `__m128i _mm_and_epi64(__m128i __a, __m128i __b)`	`VPAND xmm, xmm, xmm` VEX.128 -mavx512vl
`_mm_and_pd` `__m128d _mm_and_pd(__m128d __a, __m128d __b)`	`VPAND xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm_and_si128` `__m128i _mm_and_si128(__m128i __a, __m128i __b)`	`VPAND xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_and_epi32` `__m256i _mm256_and_epi32(__m256i __a, __m256i __b)`	`VPAND ymm, ymm, ymm` VEX.256 -mavx512vl
`_mm256_and_epi64` `__m256i _mm256_and_epi64(__m256i __a, __m256i __b)`	`VPAND ymm, ymm, ymm` VEX.256 -mavx512vl
`_mm256_and_si256` `__m256i _mm256_and_si256(__m256i __a, __m256i __b)`	`VPAND ymm, ymm, ymm` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

Masks in integer code#

Which AND the compilers pick#