VPANDN instruction (AVX, AVX2)

VPANDN inverts its first source and ANDs the result with the second, vpandn ymm0, ymm1, ymm2 computing NOT ymm1 AND ymm2, over 128 or 256 bits with no element boundaries. It is the VEX form of PANDN and belongs to the family that VPAND describes: a separate destination, a memory operand at any address, the bits above the width cleared, and no EVEX form of its own, where VPANDND and VPANDNQ take a write mask. Only the first source is inverted, and only the second may come from memory. On Zen 5, vpandn xmm8, xmm15, [mem] with 00000001h in XMM15 and FFFFFFFFh in memory gave FFFFFFFEh; with the operands the other way round, the result would have been zero. VANDNPS is the same operation under a floating-point name.

In compiled code

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 use VPANDN where a mask clears what it selects: b[i] > c[i] ? 0 : b[i] over ints is a VPCMPGTD whose result, inverted, keeps b with VPANDN. _mm256_andnot_si256(a, b) keeps the order of the instruction, inverting a.

For b[i] & ~c[i] in a loop, the two differ. Clang loads c, the operand to invert, into a register and takes b from memory with VANDNPS, as it prefers the floating-point name for a result that is only stored. GCC 14 makes all ones with VPCMPEQD, inverts c with VPXOR and ANDs with VPAND, two operations where one would do. With -march=x86-64-v4, it compiles the same loop to VPTERNLOGD with immediate 44h on zmm registers, and the intrinsic to VPANDNQ even on ymm registers.

A zeroing idiom

NOT x AND x is zero whatever x holds: vpandn xmm12, xmm6, xmm6 left all of ZMM12 zero on Zen 5. AMD’s Zen 5 guide lists VPANDN with one register twice among the zeroing idioms, which take no cycle and do not wait for the old value (Section 2.9.2), and its latency spreadsheet gives VPANDN one cycle and four per cycle otherwise. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

Forms

Every encoding of VPANDN that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPANDN xmm, xmm, m128` VPANDN_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F.WIG DF /r`	AVX
`VPANDN xmm, xmm, xmm` VPANDN_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F.WIG DF /r`	AVX
`VPANDN ymm, ymm, m256` VPANDN_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F.WIG DF /r`	AVX2
`VPANDN ymm, ymm, ymm` VPANDN_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F.WIG DF /r`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 2 and 4 quadwords in the xmm and ymm forms.

Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: ~a1&b1, ~a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    ymm1.q[i] = ~ymm2.q[i] & src3.q[i]
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPANDN xmm, xmm, xmm/m128` `VPANDN ymm, ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPANDN, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_andnot_epi32` `__m128i _mm_andnot_epi32(__m128i __A, __m128i __B)`	`VPANDN xmm, xmm, xmm` VEX.128 -mavx512vl
`_mm_andnot_epi64` `__m128i _mm_andnot_epi64(__m128i __A, __m128i __B)`	`VPANDN xmm, xmm, xmm` VEX.128 -mavx512vl
`_mm_andnot_pd` `__m128d _mm_andnot_pd(__m128d __a, __m128d __b)`	`VPANDN xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm_andnot_si128` `__m128i _mm_andnot_si128(__m128i __a, __m128i __b)`	`VPANDN xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_andnot_epi32` `__m256i _mm256_andnot_epi32(__m256i __A, __m256i __B)`	`VPANDN ymm, ymm, ymm` VEX.256 -mavx512vl
`_mm256_andnot_epi64` `__m256i _mm256_andnot_epi64(__m256i __A, __m256i __B)`	`VPANDN ymm, ymm, ymm` VEX.256 -mavx512vl
`_mm256_andnot_si256` `__m256i _mm256_andnot_si256(__m256i __a, __m256i __b)`	`VPANDN ymm, ymm, ymm` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

In compiled code#

A zeroing idiom#