VPANDQ

VPANDQ is VPANDD with quadwords: the bitwise AND of two 128-, 256- or 512-bit values, whose write mask selects quadwords and whose memory operand may be one quadword repeated to every element ({1to8} at 512 bits). The VPANDD page covers what the EVEX forms add to the VEX VPAND and how the compilers choose between the names; without a mask or a broadcast the two give the same bits.

On Zen 5, vpandq zmm7{k7}, zmm12, qword bcst [mem], with 1 in memory and E3h in the low byte of K7, kept bit 0 of quadwords 0, 1, 5, 6 and 7 and cleared the rest of them, leaving quadwords 2 to 4 of ZMM7 as they were: a test of the low bit that touches only the elements a mask selects.

Quadword constants#

A mask the width of a quadword is the usual reason for the Q:

• Low halves. q[i] & 0xffffffff over long long arrays becomes VPANDQ against a broadcast constant in GCC 14 at -O2 with -march=x86-64-v4, one instruction per eight elements.
• Bit fields. VPMULTISHIFTQB moves fields of each quadword into bytes, and VPANDQ with 1Fh in every byte clears what lies above a 5-bit field.
• 256-bit intrinsics. With -march=x86-64-v4 GCC compiles _mm256_and_si256 to vpandq ymm0, ymm0, ymm1, as the VPAND page notes, where Clang 23 emits VANDPS.

Unmasked, the name need not match the data. Clang 23 with -mavx512f swaps them: b[i] & 0xff over int arrays becomes VPANDQ and q[i] & 0xffffffff over long long arrays VPANDD, the reverse of GCC, with the same bits either way.

AMD’s Zen 5 latency spreadsheet gives the EVEX row of VPANDQ one cycle and four per cycle on any of the four vector pipes. Zen 5’s 6 recorded cases cover the register and memory forms, broadcast included, at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = zmm2.q[i] & src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPANDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB

All 686 AVX10.1 instructions