x86-64.net

Instruction

VPAVGW

Computes the rounded average of packed unsigned words.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPAVGW averages unsigned words with halves rounded up, computing (a + b + 1) >> 1 with a seventeenth bit: the VEX and EVEX form of PAVGW, whose page shows the averages compilers build without it. VPAVGB is the byte form, with the same encodings: AVX and AVX2 for VEX, AVX512BW or AVX10.1 for EVEX, with a write mask per element but no broadcast. On Zen 5, vpavgw xmm1, xmm2, xmm3 averaged 0001h and FFFFh to 8000h, 7FFFh and 0001h to 4000h and 8000h and 0001h to 4001h, and vpavgw xmm24{k2}{z}, xmm3, xmmword ptr [mem] gave BFFFh for 7FFFh and FFFFh in word 3, one of the four words K2 selects, and zeroed the other four.

In compiled code

In our builds at -O2 over fixed-size uint16_t arrays, (b[i] + c[i] + 1) >> 1 is one VPAVGW per vector in GCC 14 and Clang 23 with -march=x86-64-v3 and -march=x86-64-v4, and so is the same sum in uint32_t divided by 2. The other averages are built, as without AVX:

  • Rounding down. For (b[i] + c[i]) >> 1, Clang computes (b & c) + ((b ^ c) >> 1). GCC adds b >> 1, c >> 1 and the carry b & c & 1, which at -v4 is a single VPTERNLOGD with immediate 80h, the AND of three inputs, one of them read from memory.
  • Signed words. For int16_t, Clang uses (b | c) - ((b ^ c) >> 1) with the arithmetic VPSRAW, four instructions per vector at both levels. GCC widens to doublewords with VPMOVSXWD, adds, shifts and narrows, with VPACKUSDW and VPERMQ at -v3 and with VPERMT2W at -v4.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike two cycles, four per cycle on pipes FP0 to FP3, one more cycle than its row for VPADDW.

Forms

Every encoding of VPAVGW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPAVGW xmm, xmm, m128 VPAVGW_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG E3 /rAVX
VPAVGW xmm, xmm, xmm VPAVGW_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG E3 /rAVX
VPAVGW ymm, ymm, m256 VPAVGW_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG E3 /rAVX2
VPAVGW ymm, ymm, ymm VPAVGW_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG E3 /rAVX2
VPAVGW xmm {k}{z}, xmm, xmm VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512EVEX.128.66.0F.WIG E3 /rAVX10.1 or AVX512BW + AVX512VL
VPAVGW xmm {k}{z}, xmm, m128 VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512EVEX.128.66.0F.WIG E3 /rAVX10.1 or AVX512BW + AVX512VL
VPAVGW ymm {k}{z}, ymm, ymm VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512EVEX.256.66.0F.WIG E3 /rAVX10.1 or AVX512BW + AVX512VL
VPAVGW ymm {k}{z}, ymm, m256 VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512EVEX.256.66.0F.WIG E3 /rAVX10.1 or AVX512BW + AVX512VL
VPAVGW zmm {k}{z}, zmm, zmm VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512EVEX.512.66.0F.WIG E3 /rAVX10.1 or AVX512BW
VPAVGW zmm {k}{z}, zmm, m512 VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512EVEX.512.66.0F.WIG E3 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroingxmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, ymmno maskymm {k}{z}, ymm, ymmwith a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p011 / 0.5p017 / 0.5p011 / 0.5p011 / 0.5p018 / 0.5p011 / 1p01 / 1p08 / 1p08 / 1p0
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p013 / 0.5p0111 / 0.5p011 / 0.5p013 / 0.5p0111 / 0.5p011 / 1p03 / 1p09 / 1p011 / 1p0
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1
Zen 48 / 0.5FP0 FP1 FP2 FP32 / 1FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP12 / 11FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.25 for Zen 4 and Zen 5 (AMD 57647, row 1974; AMD 58455, row 191).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.
VPAVGW: element by elementResult word i comes from word i of xmm2 and xmm3. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.01234567xmm2a11111110k1r0r1r2r3r4r5r7xmm101234567xmm3or m128b

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result word i comes from word i of xmm2 and xmm3. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        a = zmm2.w[i]
        b = src3.w[i]
        zmm1.w[i] = (a + b + 1) >> 1
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPAVGW xmm, xmm, xmm/m128 VPAVGW ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPAVGW xmm {k}{z}, xmm, xmm/m128 VPAVGW ymm {k}{z}, ymm, ymm/m256 VPAVGW zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPAVGW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_avg_epu16 __m128i _mm_avg_epu16(__m128i __a, __m128i __b)

VPAVGW xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_avg_epu16 __m128i _mm_mask_avg_epu16(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPAVGW xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_avg_epu16 __m128i _mm_maskz_avg_epu16(__mmask8 __U, __m128i __A, __m128i __B)

VPAVGW xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_avg_epu16 __m256i _mm256_avg_epu16(__m256i __a, __m256i __b)

VPAVGW ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_avg_epu16 __m256i _mm256_mask_avg_epu16(__m256i __W, __mmask16 __U, __m256i __A, __m256i __B)

VPAVGW ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_avg_epu16 __m256i _mm256_maskz_avg_epu16(__mmask16 __U, __m256i __A, __m256i __B)

VPAVGW ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_avg_epu16 __m512i _mm512_avg_epu16(__m512i __A, __m512i __B)

VPAVGW zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_avg_epu16 __m512i _mm512_mask_avg_epu16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B)

VPAVGW zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_avg_epu16 __m512i _mm512_maskz_avg_epu16(__mmask32 __U, __m512i __A, __m512i __B)

VPAVGW zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-227 (PAVGB/PAVGW)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.