VPBLENDD

VPBLENDD picks each doubleword of its result from one of two sources by a constant: bit i of the immediate set takes element i from the third operand, clear from the second. It is the integer twin of VBLENDPS, whose page shows how blends stand in for shuffles, and came with AVX2 without a legacy SSE form: even its 128-bit form needs AVX2, where VBLENDPS needs only AVX. On Zen 5, vpblendd ymm4, ymm4, [mem], 0xB2 took doublewords 1, 4, 5 and 7 from memory and kept the others, and vpblendd xmm0, xmm13, [mem], 0x52 read only bits 3:0 of the immediate, taking element 1 from memory, and cleared bits 128 and up.

There is no EVEX form: AVX-512 blends under a mask register with VPBLENDMD, or with a merging masked move. Its other relatives choose differently: VPBLENDW by words, with its eight immediate bits repeated in each 128-bit lane, and VPBLENDVB by bytes, under a mask in a vector register.

Which blend the compilers pick#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 disagree on the name. GCC emits VPBLENDD for integer shuffles that leave every element in place, such as __builtin_shufflevector(a, b, 0, 9, 2, 11, 4, 13, 6, 15) on eight ints, and for _mm256_blend_epi32. Clang uses VBLENDPS for both, and even rewrites _mm256_blend_epi16 with immediate 0Fh, whose words pair up into doublewords, as VBLENDPS, while GCC keeps VPBLENDW. Setting element 0 of an int vector, a[0] = x, turns the tables: Clang moves x in with VMOVD and blends it with vpblendd ymm0, ymm0, ymm1, 1, and GCC uses VPINSRD and VINSERTI128.

VPBLENDD also joins halves inside longer sequences: both compilers use it to merge the high doublewords of even and odd products in a division by a constant (see VPMULDQ), and GCC in its byte multiply (see VPUNPCKHBW).

AMD’s latency spreadsheet for Zen 5 gives VPBLENDD one cycle and four per cycle on any of the four vector pipes, the same as VBLENDPS, where VPBLENDVB runs on two. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if imm8 >> i & 1:
        ymm1.d[i] = src3.d[i]
    else:
        ymm1.d[i] = ymm2.d[i]
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBLENDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD

All 138 AVX2 instructions