VPBLENDMD

VPBLENDMD builds each doubleword of its destination from one of two sources, chosen by a mask register: the second source where the mask bit is set, the first where it is clear, or zero there with {z}. Without a mask (k0) it copies the second source. The second source may be memory or a broadcast element. The result goes to a third register, which is what sets it apart from a merge-masked move: vmovdqa32 zmm0{k1}, zmm1 keeps the elements of its own destination where the mask is clear, so the fallback values must already be there. VPBLENDMD names the fallback separately and leaves both sources intact.

It replaces SSE4.1’s PBLENDVB and AVX’s VPBLENDVB, whose selector is a vector of top bits, and the immediate selector of VPBLENDD, which is fixed when the code is written; here the selector is the mask a compare such as VPCMPD or VPTESTMD has just written.

In compiled code#

_mm512_mask_blend_epi32(k, a, b) takes b where k is set and a elsewhere. GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile it to vmovdqa32 zmm0{k1}, zmm1 when the result may replace a, and to VPBLENDMD when it must land in b’s register; with b in memory both use a masked load, VMOVDQU32, instead. A select in a loop is where VPBLENDMD appears: Clang vectorizes o[i] = a[i] ? 7 : o[i] to VPTESTNMD and a VPBLENDMD that takes the old o[i] straight from memory. A blend of the larger elements under a greater-than mask Clang recognizes as VPMAXSD.

Intel’s optimization manual blends with it in its top-K search (Section 8.5.4, Example 8-14): a KSHIFT and KXOR of a compare’s mask leave one bit, and VBLENDMPS and VPBLENDMD write the new score and its index into that slot. AMD’s Zen 5 guide lists VPBLENDMD as one macro-op with a latency of one cycle on any of the four vector pipes, as for VPBLENDD.

VPBLENDMQ blends quadwords, AVX512BW’s VPBLENDMB and VPBLENDMW bytes and words, and VBLENDMPS singles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    else:
        zmm1.d[i] = zmm2.d[i]
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

opmask selects the source

Memory forms

embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ

All 686 AVX10.1 instructions