Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

VPBLENDMQ builds each quadword of its destination from one of two sources, chosen by a mask register: the second source where the mask bit is set, the first where it is clear, or zero there with {z}. It is the quadword form of VPBLENDMD, whose page sets it against masked moves and the older blends. With at most eight quadwords it reads only the low 8 bits of the mask.

Recorded on Zen 5

  • The low byte of the mask. In vpblendmq zmm0{k7}, zmm31, zmm16 K7 held EBB9F4D13D1DF2E3h; its low byte, E3h, took quadwords 0, 1 and 5 to 7 from ZMM16 and 2 to 4 from ZMM31, and none of the old ZMM0 survived.
  • Broadcast. vpblendmq zmm17{k3}, zmm30, qword bcst [mem] wrote the memory quadword into the six elements where EBh, the low byte of K3, has a bit set, and ZMM30’s quadwords 2 and 4 into the others.
  • Narrow forms use fewer bits: vpblendmq ymm17{k5}, ymm30, ymmword ptr [mem] took only element 0 from memory, by bits 3:0 of K5, and cleared bits 256 and up.

In compiled code

_mm512_mask_blend_epi64(k, a, b) takes b where k is set. GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile it as the word form on VPBLENDMW’s page: a masked move or load when the result may replace a or b is in memory, VPBLENDMQ when the operands come the other way round. Neither folds a broadcast: with _mm512_set1_epi64(*p) as an operand both broadcast first with VPBROADCASTQ and then move under the mask.

A select with a constant fallback is where both emit it. For o[i] = a[i] > b[i] ? c[i] : 5 over int64_t arrays, both compare into a mask register, GCC with VPCMPQ and Clang with the EVEX VPCMPGTQ, and blend a vector of fives with c[i] read straight from memory, GCC on ZMM registers and Clang on YMM. For o[i] = a[i] ? 7 : o[i] they part as for words: GCC blends with VPBLENDMQ, Clang marks the nonzero elements with VPTESTMQ and stores sevens with a masked VMOVDQU64.

AMD’s Zen 5 latency spreadsheet gives VPBLENDMQ one cycle and four per cycle on any of the four vector pipes, as VPBLENDMD. The 6 recorded cases cover the register, memory and broadcast forms at all three widths.

Forms

Every encoding of VPBLENDMQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPBLENDMQ zmm {k}{z}, zmm, zmm VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512EVEX.512.66.0F38.W1 64 /rAVX10.1 or AVX512F
VPBLENDMQ zmm {k}{z}, zmm, m512/m64bcst VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F38.W1 64 /rAVX10.1 or AVX512F
VPBLENDMQ xmm {k}{z}, xmm, xmm VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F38.W1 64 /rAVX10.1 or AVX512F + AVX512VL
VPBLENDMQ xmm {k}{z}, xmm, m128/m64bcst VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F38.W1 64 /rAVX10.1 or AVX512F + AVX512VL
VPBLENDMQ ymm {k}{z}, ymm, ymm VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512EVEX.256.66.0F38.W1 64 /rAVX10.1 or AVX512F + AVX512VL
VPBLENDMQ ymm {k}{z}, ymm, m256/m64bcst VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F38.W1 64 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m64bcstxmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm
xmm {k}{z}, xmm, m128/m64bcstymm {k}{z}, ymm, m256/m64bcst
Skylake-SP, Ice Lake2 / 0.5p058 / 0.5p0151 / 0.33p0157 / 0.5p0158 / 0.5p015
Sapphire Rapids1 / 0.5p059 / 0.5p051 / 0.33p0158 / 0.33p0159 / 0.33p015
Zen 41 / 1FP0 FP38 / 1FP0 FP31 / 0.51FP0 FP38 / 0.5FP0 FP38 / 0.5FP0 FP3
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.25 for Zen 4 and Zen 5 (AMD 57647, row 1986; AMD 58455, row 442).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by mask: each quadword comes from xmm3 where its bit of k1 is 1; elsewhere merging takes it from xmm2, and zeroing writes 0.

merging, {k1}

VPBLENDMQ with merging, {k1}With merging: result quadwords 1 to 0: b1, a0.01xmm2a10k1a0b1xmm101xmm3or m128b

zeroing, {k1}{z}

VPBLENDMQ with zeroing, {k1}{z}With zeroing: result quadwords 1 to 0: b1, 0.0110k10b1xmm101xmm3or m128b

Example mask k1 = 0x02. Every quadword of the wider forms works alike. With m64bcst, one quadword from memory stands for every element of xmm3.

With merging: result quadwords 1 to 0: b1, a0.

With zeroing: result quadwords 1 to 0: b1, 0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    else:
        zmm1.q[i] = zmm2.q[i]
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPBLENDMQ xmm {k}{z}, xmm, xmm/m128/m64bcst VPBLENDMQ ymm {k}{z}, ymm, ymm/m256/m64bcst VPBLENDMQ zmm {k}{z}, zmm, zmm/m512/m64bcst
xmm, ymm, zmmexplicitwrite
{k}explicitread (selector)
xmm, ymm, zmmexplicitread
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms
opmask selects the source
Memory forms
embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-439 (VPBLENDMD/VPBLENDMQ)
  6. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.