x86-64.net

Instruction

VPBLENDMW

Picks each word from the second source where a mask bit is set, otherwise from the first.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPBLENDMW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPBLENDMW xmm {k}{z}, xmm, xmm VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512EVEX.128.66.0F38.W1 66 /rAVX10.1 or AVX512BW + AVX512VL
VPBLENDMW xmm {k}{z}, xmm, m128 VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512EVEX.128.66.0F38.W1 66 /rAVX10.1 or AVX512BW + AVX512VL
VPBLENDMW ymm {k}{z}, ymm, ymm VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512EVEX.256.66.0F38.W1 66 /rAVX10.1 or AVX512BW + AVX512VL
VPBLENDMW ymm {k}{z}, ymm, m256 VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512EVEX.256.66.0F38.W1 66 /rAVX10.1 or AVX512BW + AVX512VL
VPBLENDMW zmm {k}{z}, zmm, zmm VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512EVEX.512.66.0F38.W1 66 /rAVX10.1 or AVX512BW
VPBLENDMW zmm {k}{z}, zmm, m512 VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512EVEX.512.66.0F38.W1 66 /rAVX10.1 or AVX512BW

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.