VPBLENDMW

VPBLENDMW builds each word of its destination from one of two sources, chosen by a mask register: the second source where the mask bit is set, the first where it is clear, or zero there with {z}. It is the word form of VPBLENDMD, whose page sets it against masked moves and the older blends, and needs AVX512BW. Words have no broadcast form, so the second source is a register or a full vector in memory.

Recorded on Zen 5#

• The first source is the fallback. vpblendmw zmm17{k1}, zmm30, zmm2 took ZMM2’s word where K1 had a bit set and ZMM30’s elsewhere; none of the old ZMM17 survived, although the mask is written as merging.
• Zeroing. vpblendmw ymm17{k2}{z}, ymm30, ymm2 took YMM2’s words at the bits set in F2C9h, the low 16 bits of K2, and wrote 0 to the other seven words.
• No mask copies the second source: {evex} vpblendmw ymm5, ymm5, ymmword ptr [mem] loaded memory.

In compiled code#

_mm512_mask_blend_epi16(k, a, b) takes b where k is set. GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile it to vmovdqu16 zmm0{k1}, zmm1 when the result may replace a, and with b in memory to a masked load; with the operands the other way round they emit VPBLENDMW. In loops over short arrays the two compilers differ. For o[i] = a[i] ? 7 : o[i], GCC marks the zero elements with VPCMPW and blends a vector of sevens with o read straight from memory by VPBLENDMW, while Clang marks the nonzero ones with VPTESTMW and writes sevens with a masked VMOVDQU16 store, leaving the rest of o untouched. For o[i] = a[i] > b[i] ? c[i] : b[i] both load b and overwrite it with a masked VMOVDQU16 load of c.

AMD’s Zen 5 latency spreadsheet gives VPBLENDMW one cycle and four per cycle on any of the four vector pipes, as VPBLENDMD. Zen 5’s 6 recorded cases cover the register and memory forms at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = src3.w[i]
    elif zeroing:
        zmm1.w[i] = 0
    else:
        zmm1.w[i] = zmm2.w[i]
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

opmask selects the source

Memory forms

memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD

All 686 AVX10.1 instructions