VPBLENDVB instruction (AVX, AVX2)

VPBLENDVB is the VEX form of PBLENDVB, whose page explains the byte select by the top bit of each mask byte and how SSE2 code did without it. The VEX form names the mask as a fourth register, in bits 7:4 of an immediate byte, instead of the implied XMM0; it leaves both sources intact, and with AVX2 it selects 32 bytes in a YMM register (the 128-bit form needs only AVX). The cases recorded on Zen 5 used registers in several roles: vpblendvb ymm7, ymm11, ymmword ptr [mem], ymm7 took its mask from the old value of its destination, and vpblendvb xmm4, xmm4, xmm4, xmm4 gave XMM4 back unchanged and cleared bits 128 and up.

Elements of any size

The mask is read per byte, so the instruction selects elements of any size when the mask comes from a compare of that size. GCC 14 at -O2 with -march=x86-64-v3 uses it for a[i] > b[i] ? a[i] : 7 over int after a VPCMPGTD, and over int16_t after a VPCMPGTW. Clang 23 uses it for words and bytes but VBLENDVPS for doublewords. For bytes chosen by the sign of a third array, c[i] < 0 ? p[i] : q[i], Clang passes the bytes of c straight in as the mask, while GCC first compares them with zero by VPCMPGTB.

No EVEX form

AVX-512 selects under a mask register instead, and VPBLENDVB cannot reach registers 16 to 31. With -march=x86-64-v4 the compares in these loops write mask registers: GCC then selects bytes with VPBLENDMB on ZMM registers and doublewords with VPBLENDMD, and Clang uses a merging masked VMOVDQU8 on YMM registers. _mm256_blendv_epi8 still compiles to one VPBLENDVB in both.

AMD’s latency spreadsheet for Zen 5 lists VPBLENDVB as one macro-op with a latency of one cycle on two pipes, FP1 and FP2, where the blends by an immediate, VPBLENDW and VPBLENDD, run on all four.

Forms

Every encoding of VPBLENDVB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPBLENDVB xmm, xmm, m128, xmm` VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq	`VEX.128.66.0F3A.W0 4C /r /is4`	AVX
`VPBLENDVB xmm, xmm, xmm, xmm` VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F3A.W0 4C /r /is4`	AVX
`VPBLENDVB ymm, ymm, m256, ymm` VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq	`VEX.256.66.0F3A.W0 4C /r /is4`	AVX2
`VPBLENDVB ymm, ymm, ymm, ymm` VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F3A.W0 4C /r /is4`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by vector: each byte comes from xmm3 where the sign bit of the byte in the same place of xmm4 is 1, else from xmm2.

Example sign bits of xmm4: 0000000010110010. Every byte of the wider forms works alike.

Result bytes 15 to 0: a15, a14, a13, a12, a11, a10, a9, a8, b7, a6, b5, b4, a3, a2, b1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if ymm4.b[i] >> 7:
        ymm1.b[i] = src3.b[i]
    else:
        ymm1.b[i] = ymm2.b[i]
# ymm4.b[i] >> 7: the sign bit of the element
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPBLENDVB xmm, xmm, xmm/m128, xmm` `VPBLENDVB ymm, ymm, ymm/m256, ymm`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`xmm, ymm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBLENDVB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blendv_epi8` `__m128i _mm_blendv_epi8(__m128i __V1, __m128i __V2, __m128i __M)`	`VPBLENDVB xmm, xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_blendv_epi8` `__m256i _mm256_blendv_epi8(__m256i __V1, __m256i __V2, __m256i __M)`	`VPBLENDVB ymm, ymm, ymm, ymm` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

Elements of any size#

No EVEX form#