VPBLENDW instruction (AVX, AVX2)

Forms

Every encoding of VPBLENDW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPBLENDW xmm, xmm, m128, imm8` VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb	`VEX.128.66.0F3A.WIG 0E /r ib`	AVX
`VPBLENDW xmm, xmm, xmm, imm8` VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb	`VEX.128.66.0F3A.WIG 0E /r ib`	AVX
`VPBLENDW ymm, ymm, m256, imm8` VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb	`VEX.256.66.0F3A.WIG 0E /r ib`	AVX2
`VPBLENDW ymm, ymm, ymm, imm8` VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb	`VEX.256.66.0F3A.WIG 0E /r ib`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by immediate: each word comes from xmm3 where its bit of imm8 is 1, else from xmm2.

Example: imm8 = 0xB2 (1011 0010 in binary). The ymm form repeats this in each 128-bit lane, with the same bits of imm8.

Result words 7 to 0: b7, a6, b5, b4, a3, a2, b1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if imm8 >> i % 8 & 1:
        ymm1.w[i] = src3.w[i]
    else:
        ymm1.w[i] = ymm2.w[i]
# the same 8 bits of imm8 in each lane
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPBLENDW xmm, xmm, xmm/m128, imm8` `VPBLENDW ymm, ymm, ymm/m256, imm8`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBLENDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blend_epi16` `__m128i _mm_blend_epi16(__m128i V1, __m128i V2, const int M)`	`VPBLENDW xmm, xmm, xmm, imm8` VEX.128 -mavxwith AVX enabled
`_mm256_blend_epi16` `__m256i _mm256_blend_epi16(__m256i V1, __m256i V2, const int M)`	`VPBLENDW ymm, ymm, ymm, imm8` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions