x86-64.net

Instruction

VPBROADCASTB

Copies one byte from a register or memory to every byte of a vector.

Extensions
Forms
13 (4 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPBROADCASTB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPBROADCASTB xmm, m8 VPBROADCASTB_XMMdq_MEMbVEX.128.66.0F38.W0 78 /rAVX2
VPBROADCASTB xmm, xmm VPBROADCASTB_XMMdq_XMMbVEX.128.66.0F38.W0 78 /rAVX2
VPBROADCASTB ymm, m8 VPBROADCASTB_YMMqq_MEMbVEX.256.66.0F38.W0 78 /rAVX2
VPBROADCASTB ymm, xmm VPBROADCASTB_YMMqq_XMMbVEX.256.66.0F38.W0 78 /rAVX2
VPBROADCASTB xmm {k}{z}, xmm VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512EVEX.128.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB xmm {k}{z}, m8 VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512EVEX.128.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB xmm {k}{z}, r32 VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512EVEX.128.66.0F38.W0 7A /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB ymm {k}{z}, xmm VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512EVEX.256.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB ymm {k}{z}, m8 VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512EVEX.256.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB ymm {k}{z}, r32 VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512EVEX.256.66.0F38.W0 7A /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB zmm {k}{z}, xmm VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512EVEX.512.66.0F38.W0 78 /rAVX10.1 or AVX512BW
VPBROADCASTB zmm {k}{z}, m8 VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512EVEX.512.66.0F38.W0 78 /rAVX10.1 or AVX512BW
VPBROADCASTB zmm {k}{z}, r32 VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512EVEX.512.66.0F38.W0 7A /rAVX10.1 or AVX512BW

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_broadcastb_epi8 __m128i _mm_broadcastb_epi8(__m128i __X)

VPBROADCASTB xmm, xmm VEX.128 -mavx2

_mm_mask_broadcastb_epi8 __m128i _mm_mask_broadcastb_epi8(__m128i __O, __mmask16 __M, __m128i __A)

VPBROADCASTB xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_mask_set1_epi8 __m128i _mm_mask_set1_epi8(__m128i __O, __mmask16 __M, char __A)

VPBROADCASTB xmm {k}, r32 EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_broadcastb_epi8 __m128i _mm_maskz_broadcastb_epi8(__mmask16 __M, __m128i __A)

VPBROADCASTB xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_set1_epi8 __m128i _mm_maskz_set1_epi8(__mmask16 __M, char __A)

VPBROADCASTB xmm {k}{z}, r32 EVEX.128 -mavx512vl -mavx512bw

_mm256_broadcastb_epi8 __m256i _mm256_broadcastb_epi8(__m128i __X)

VPBROADCASTB ymm, xmm VEX.256 -mavx2

_mm256_mask_broadcastb_epi8 __m256i _mm256_mask_broadcastb_epi8(__m256i __O, __mmask32 __M, __m128i __A)

VPBROADCASTB ymm {k}, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_set1_epi8 __m256i _mm256_mask_set1_epi8(__m256i __O, __mmask32 __M, char __A)

VPBROADCASTB ymm {k}, r32 EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_broadcastb_epi8 __m256i _mm256_maskz_broadcastb_epi8(__mmask32 __M, __m128i __A)

VPBROADCASTB ymm {k}{z}, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_set1_epi8 __m256i _mm256_maskz_set1_epi8(__mmask32 __M, char __A)

VPBROADCASTB ymm {k}{z}, r32 EVEX.256 -mavx512vl -mavx512bw

_mm512_broadcastb_epi8 __m512i _mm512_broadcastb_epi8(__m128i __A)

VPBROADCASTB zmm, xmm EVEX.512 -mavx512bw

_mm512_mask_broadcastb_epi8 __m512i _mm512_mask_broadcastb_epi8(__m512i __O, __mmask64 __M, __m128i __A)

VPBROADCASTB zmm {k}, xmm EVEX.512 -mavx512bw

_mm512_mask_set1_epi8 __m512i _mm512_mask_set1_epi8(__m512i __O, __mmask64 __M, char __A)

VPBROADCASTB zmm {k}, r32 EVEX.512 -mavx512bw

_mm512_maskz_broadcastb_epi8 __m512i _mm512_maskz_broadcastb_epi8(__mmask64 __M, __m128i __A)

VPBROADCASTB zmm {k}{z}, xmm EVEX.512 -mavx512bw

_mm512_maskz_set1_epi8 __m512i _mm512_maskz_set1_epi8(__mmask64 __M, char __A)

VPBROADCASTB zmm {k}{z}, r32 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.