Instruction
VPBROADCASTB
Copies one byte from a register or memory to every byte of a vector.
VPBROADCASTB copies one byte to every byte of a vector: 16, 32 or 64 copies of the low byte of an XMM register, of a byte in memory, or, in the EVEX forms of AVX512BW, of the low byte of a general-purpose register. VPBROADCASTD describes the family and how the sources differ by encoding; this page is about what bytes are broadcast for.
A character to compare against
Byte-oriented vector code nearly always starts by spreading a run-time
byte across a register: the character that memchr or strchr looks
for, a delimiter to split on, a byte to count or to fill with. Each
block of input is then compared with VPCMPEQB, and
the matches leave the register with VPMOVMSKB or
as a mask register. For _mm256_set1_epi8(c), GCC 14 and Clang 23 at
-O2 emit VMOVD and VPBROADCASTB for -march=x86-64-v3,
and VPBROADCASTB straight from the register for x86-64-v4. Clang
vectorizes a loop counting the bytes equal to c this way, and GCC
fills an array with c from a ZMM register made by
vpbroadcastb zmm0, esi at x86-64-v4.
Before AVX2 there was no byte broadcast: SSSE3 code does it with PSHUFB and an all-zero selector, and for SSE2 both compilers need three shuffles after the MOVD, starting with PUNPCKLBW and ending with PSHUFD.
Not for constants
Neither compiler uses VPBROADCASTB for a constant such as
_mm256_set1_epi8(0x0f): since every byte is the same, any wider
element is the same too. GCC builds 0F0F0F0Fh in a general-purpose
register and broadcasts it with VPBROADCASTD; Clang broadcasts 8 bytes
from memory with VBROADCASTSD, or applies them
as an embedded broadcast {1to4} with AVX-512. The memory form of
VPBROADCASTB is still useful when the byte comes from memory: it reads
just that byte, with no alignment requirement, so it cannot touch the
bytes around it.
AMD’s Zen 5 guide lists the forms with an XMM or memory source as one macro-op with a latency of one cycle, and the form with a general-purpose register source as two macro-ops.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPBROADCASTB xmm, m8
VPBROADCASTB_XMMdq_MEMb | VEX.128.66.0F38.W0 78 /r | AVX2 |
VPBROADCASTB xmm, xmm
VPBROADCASTB_XMMdq_XMMb | VEX.128.66.0F38.W0 78 /r | AVX2 |
VPBROADCASTB ymm, m8
VPBROADCASTB_YMMqq_MEMb | VEX.256.66.0F38.W0 78 /r | AVX2 |
VPBROADCASTB ymm, xmm
VPBROADCASTB_YMMqq_XMMb | VEX.256.66.0F38.W0 78 /r | AVX2 |
VPBROADCASTB xmm {k}{z}, xmm
VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 | EVEX.128.66.0F38.W0 78 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTB xmm {k}{z}, m8
VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 | EVEX.128.66.0F38.W0 78 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTB xmm {k}{z}, r32
VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 | EVEX.128.66.0F38.W0 7A /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTB ymm {k}{z}, xmm
VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 | EVEX.256.66.0F38.W0 78 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTB ymm {k}{z}, m8
VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 | EVEX.256.66.0F38.W0 78 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTB ymm {k}{z}, r32
VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 | EVEX.256.66.0F38.W0 7A /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTB zmm {k}{z}, xmm
VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 | EVEX.512.66.0F38.W0 78 /r | AVX10.1 or AVX512BW |
VPBROADCASTB zmm {k}{z}, m8
VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 | EVEX.512.66.0F38.W0 78 /r | AVX10.1 or AVX512BW |
VPBROADCASTB zmm {k}{z}, r32
VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 | EVEX.512.66.0F38.W0 7A /r | AVX10.1 or AVX512BW |
Latency and throughput
| Model | xmm, m8xmm {k}{z}, m8no mask | xmm, xmm | ymm, m8 | ymm, xmmymm {k}{z}, xmmno maskzmm {k}{z}, xmmno mask | xmm {k}{z}, xmmno mask | xmm {k}{z}, xmmwith a mask, zeroing | xmm {k}{z}, m8with a mask, zeroing | xmm {k}{z}, r32 | ymm {k}{z}, xmmwith a mask, zeroingymm {k}{z}, r32zmm {k}{z}, xmmwith a mask, zeroingzmm {k}{z}, r32 | ymm {k}{z}, m8no maskzmm {k}{z}, m8no mask | ymm {k}{z}, m8with a mask, zeroingzmm {k}{z}, m8with a mask, zeroing |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Haswell, Broadwell | 9 / 1p015 | 3 / 1p5 | 9 / 1p015 | 3 / 1p5 | |||||||
| Skylake | 7 / 1p5 | 3 / 1p5 | 8 / 1p5 | 3 / 1p5 | |||||||
| Skylake-SP, Ice Lake | 7 / 1p5 | 3 / 1p5 | 8 / 1p5 | 3 / 1p5 | 1 / 1p5 | 1 / 1p5 | 7 / 1p5 | 1 / 1p5 | 3 / 1p5 | 8 / 1p5 | 8 / 1p5 |
| Alder Lake | 8 / 1p5 | 1 / 1p5 | 9 / 1p5 | 3 / 1p5 | |||||||
| Sapphire Rapids | 8 / 1p5 | 1 / 1p5 | 9 / 1p5 | 3 / 1p5 | 1 / 1p5 | 3 / 1p5 | 11 / 1p5 | 5 / 1p5 | 5 / 1p5 | 9 / 1p5 | 11 / 1p5 |
| Lunar Lake | 8 / 0.5V2 V3 | 1 / 0.33p135 | 8 / 2.33V2 V3 | 3 / 0.5V2 V3 | |||||||
| Zen | 8 / 1FPU1 FPU2 | 1 / 0.5FPU1 FPU2 | 8 / 2FPU1 | 2 / 1FPU1 FPU2 | |||||||
| Zen 2 | 8 / 1FPU1 FPU2 | 1 / 0.5FPU1 FPU2 | 8 / 2FPU1 | 2 / 0.5FPU1 FPU2 | |||||||
| Zen 3 | 8 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 2 / 1FP1 | |||||||
| Zen 4 | 8 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 1 / 11FP1 | 1 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 1 / 0.52FP1 FP2 | 1 / 1FP1 | 8 / 1FP1 | 8 / 1FP1 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown for the xmm form; the ymm and zmm forms work the same on 32 and 64 bytes. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result bytes 15 to 0: a0, unchanged (bit 14 of k1 is 0), a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 8):
if k1[i]: # 1 without a write mask
zmm1.b[i] = src2.b[0]
elif zeroing:
zmm1.b[i] = 0
# else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 13 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPBROADCASTB xmm, xmm/m8 VPBROADCASTB ymm, xmm/m8 | ||
xmm, ymm | explicit | write |
xmm/m8 | explicit | read |
VPBROADCASTB xmm {k}{z}, xmm/m8 VPBROADCASTB ymm {k}{z}, xmm/m8 VPBROADCASTB zmm {k}{z}, xmm/m8 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m8 | explicit | read |
VPBROADCASTB xmm {k}{z}, r32 VPBROADCASTB ymm {k}{z}, r32 VPBROADCASTB zmm {k}{z}, r32 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
r32 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- VEX forms
avx-type-6VPBROADCASTB xmm {k}{z}, xmm/m8VPBROADCASTB ymm {k}{z}, xmm/m8VPBROADCASTB zmm {k}{z}, xmm/m8AVX512-E6VPBROADCASTB xmm {k}{z}, r32VPBROADCASTB ymm {k}{z}, r32VPBROADCASTB zmm {k}{z}, r32AVX512-E7NM
Attributes
What else XED records about the forms. How to read.
- EVEX forms
- write masking
- EVEX memory forms
- memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_broadcastb_epi8
__m128i _mm_broadcastb_epi8(__m128i __X) |
|
_mm_mask_broadcastb_epi8
__m128i _mm_mask_broadcastb_epi8(__m128i __O, __mmask16 __M, __m128i __A) |
|
_mm_mask_set1_epi8
__m128i _mm_mask_set1_epi8(__m128i __O, __mmask16 __M, char __A) |
|
_mm_maskz_broadcastb_epi8
__m128i _mm_maskz_broadcastb_epi8(__mmask16 __M, __m128i __A) |
|
_mm_maskz_set1_epi8
__m128i _mm_maskz_set1_epi8(__mmask16 __M, char __A) |
|
_mm256_broadcastb_epi8
__m256i _mm256_broadcastb_epi8(__m128i __X) |
|
_mm256_mask_broadcastb_epi8
__m256i _mm256_mask_broadcastb_epi8(__m256i __O, __mmask32 __M, __m128i __A) |
|
_mm256_mask_set1_epi8
__m256i _mm256_mask_set1_epi8(__m256i __O, __mmask32 __M, char __A) |
|
_mm256_maskz_broadcastb_epi8
__m256i _mm256_maskz_broadcastb_epi8(__mmask32 __M, __m128i __A) |
|
_mm256_maskz_set1_epi8
__m256i _mm256_maskz_set1_epi8(__mmask32 __M, char __A) |
|
_mm512_broadcastb_epi8
__m512i _mm512_broadcastb_epi8(__m128i __A) |
|
_mm512_mask_broadcastb_epi8
__m512i _mm512_mask_broadcastb_epi8(__m512i __O, __mmask64 __M, __m128i __A) |
|
_mm512_mask_set1_epi8
__m512i _mm512_mask_set1_epi8(__m512i __O, __mmask64 __M, char __A) |
|
_mm512_maskz_broadcastb_epi8
__m512i _mm512_maskz_broadcastb_epi8(__mmask64 __M, __m128i __A) |
|
_mm512_maskz_set1_epi8
__m512i _mm512_maskz_set1_epi8(__mmask64 __M, char __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX2 | AVX2 | Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 |
AVX512BW_128 | AVX10.1 or AVX512BW + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6 |
AVX512BW_256 | Same as AVX512BW_128 | Same as AVX512BW_128 |
AVX512BW_512 | AVX10.1 or AVX512BW | Same as AVX512BW_128 |
More AVX2 instructions
- VPACKSSDW
- VPACKSSWB
- VPACKUSDW
- VPACKUSWB
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDD
- VPBLENDVB
- VPBLENDW
- VPBROADCASTD
- VPBROADCASTQ
- VPBROADCASTW
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPERM2I128
- VPERMD
- VPERMPD
- VPERMPS
- VPERMQ
- VPGATHERDD
- VPGATHERDQ
- VPGATHERQD
- VPGATHERQQ
More AVX10.1 instructions
- VPACKUSWB
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPANDD
- VPANDND
- VPANDNQ
- VPANDQ
- VPAVGB
- VPAVGW
- VPBLENDMB
- VPBLENDMD
- VPBLENDMQ
- VPBLENDMW
- VPBROADCASTD
- VPBROADCASTMB2Q
- VPBROADCASTMW2D
- VPBROADCASTQ
- VPBROADCASTW
- VPCLMULQDQ
- VPCMPB
- VPCMPD
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPQ
- VPCMPUB
- VPCMPUD
- VPCMPUQ
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-442 (VPBROADCAST); Volume 2C, page 5-451 (VPBROADCASTB/
W/ D/ Q) - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.