Extensions
Forms
13 (4 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

VPBROADCASTB copies one byte to every byte of a vector: 16, 32 or 64 copies of the low byte of an XMM register, of a byte in memory, or, in the EVEX forms of AVX512BW, of the low byte of a general-purpose register. VPBROADCASTD describes the family and how the sources differ by encoding; this page is about what bytes are broadcast for.

A character to compare against

Byte-oriented vector code nearly always starts by spreading a run-time byte across a register: the character that memchr or strchr looks for, a delimiter to split on, a byte to count or to fill with. Each block of input is then compared with VPCMPEQB, and the matches leave the register with VPMOVMSKB or as a mask register. For _mm256_set1_epi8(c), GCC 14 and Clang 23 at -O2 emit VMOVD and VPBROADCASTB for -march=x86-64-v3, and VPBROADCASTB straight from the register for x86-64-v4. Clang vectorizes a loop counting the bytes equal to c this way, and GCC fills an array with c from a ZMM register made by vpbroadcastb zmm0, esi at x86-64-v4.

Before AVX2 there was no byte broadcast: SSSE3 code does it with PSHUFB and an all-zero selector, and for SSE2 both compilers need three shuffles after the MOVD, starting with PUNPCKLBW and ending with PSHUFD.

Not for constants

Neither compiler uses VPBROADCASTB for a constant such as _mm256_set1_epi8(0x0f): since every byte is the same, any wider element is the same too. GCC builds 0F0F0F0Fh in a general-purpose register and broadcasts it with VPBROADCASTD; Clang broadcasts 8 bytes from memory with VBROADCASTSD, or applies them as an embedded broadcast {1to4} with AVX-512. The memory form of VPBROADCASTB is still useful when the byte comes from memory: it reads just that byte, with no alignment requirement, so it cannot touch the bytes around it.

AMD’s Zen 5 guide lists the forms with an XMM or memory source as one macro-op with a latency of one cycle, and the form with a general-purpose register source as two macro-ops.

Forms

Every encoding of VPBROADCASTB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPBROADCASTB xmm, m8 VPBROADCASTB_XMMdq_MEMbVEX.128.66.0F38.W0 78 /rAVX2
VPBROADCASTB xmm, xmm VPBROADCASTB_XMMdq_XMMbVEX.128.66.0F38.W0 78 /rAVX2
VPBROADCASTB ymm, m8 VPBROADCASTB_YMMqq_MEMbVEX.256.66.0F38.W0 78 /rAVX2
VPBROADCASTB ymm, xmm VPBROADCASTB_YMMqq_XMMbVEX.256.66.0F38.W0 78 /rAVX2
VPBROADCASTB xmm {k}{z}, xmm VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512EVEX.128.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB xmm {k}{z}, m8 VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512EVEX.128.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB xmm {k}{z}, r32 VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512EVEX.128.66.0F38.W0 7A /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB ymm {k}{z}, xmm VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512EVEX.256.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB ymm {k}{z}, m8 VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512EVEX.256.66.0F38.W0 78 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB ymm {k}{z}, r32 VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512EVEX.256.66.0F38.W0 7A /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTB zmm {k}{z}, xmm VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512EVEX.512.66.0F38.W0 78 /rAVX10.1 or AVX512BW
VPBROADCASTB zmm {k}{z}, m8 VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512EVEX.512.66.0F38.W0 78 /rAVX10.1 or AVX512BW
VPBROADCASTB zmm {k}{z}, r32 VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512EVEX.512.66.0F38.W0 7A /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m8
xmm {k}{z}, m8no mask
xmm, xmmymm, m8ymm, xmm
ymm {k}{z}, xmmno mask
zmm {k}{z}, xmmno mask
xmm {k}{z}, xmmno maskxmm {k}{z}, xmmwith a mask, zeroingxmm {k}{z}, m8with a mask, zeroingxmm {k}{z}, r32ymm {k}{z}, xmmwith a mask, zeroing
ymm {k}{z}, r32
zmm {k}{z}, xmmwith a mask, zeroing
zmm {k}{z}, r32
ymm {k}{z}, m8no mask
zmm {k}{z}, m8no mask
ymm {k}{z}, m8with a mask, zeroing
zmm {k}{z}, m8with a mask, zeroing
Haswell, Broadwell9 / 1p0153 / 1p59 / 1p0153 / 1p5
Skylake7 / 1p53 / 1p58 / 1p53 / 1p5
Skylake-SP, Ice Lake7 / 1p53 / 1p58 / 1p53 / 1p51 / 1p51 / 1p57 / 1p51 / 1p53 / 1p58 / 1p58 / 1p5
Alder Lake8 / 1p51 / 1p59 / 1p53 / 1p5
Sapphire Rapids8 / 1p51 / 1p59 / 1p53 / 1p51 / 1p53 / 1p511 / 1p55 / 1p55 / 1p59 / 1p511 / 1p5
Lunar Lake8 / 0.5V2 V31 / 0.33p1358 / 2.33V2 V33 / 0.5V2 V3
Zen8 / 1FPU1 FPU21 / 0.5FPU1 FPU28 / 2FPU12 / 1FPU1 FPU2
Zen 28 / 1FPU1 FPU21 / 0.5FPU1 FPU28 / 2FPU12 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP1
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 11FP11 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.52FP1 FP21 / 1FP18 / 1FP18 / 1FP1
  1. Zen 4 model, ymm form: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2003; AMD 58455, row 1292).
  2. Zen 4 model: AMD's spreadsheets give reciprocal throughput 1 for Zen 4 and Zen 5 (AMD 57647, row 1996; AMD 58455, row 507).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: the low byte goes to every byte of the result.
VPBROADCASTB: one byte everywhereResult bytes 15 to 0: a0, unchanged (bit 14 of k1 is 0), a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.0123456789101112131415xmm2or r32, m8a1111111111111110k1a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0xmm1

Shown for the xmm form; the ymm and zmm forms work the same on 32 and 64 bytes. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result bytes 15 to 0: a0, unchanged (bit 14 of k1 is 0), a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        zmm1.b[i] = src2.b[0]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 13 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPBROADCASTB xmm, xmm/m8 VPBROADCASTB ymm, xmm/m8
xmm, ymmexplicitwrite
xmm/m8explicitread
VPBROADCASTB xmm {k}{z}, xmm/m8 VPBROADCASTB ymm {k}{z}, xmm/m8 VPBROADCASTB zmm {k}{z}, xmm/m8
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m8explicitread
VPBROADCASTB xmm {k}{z}, r32 VPBROADCASTB ymm {k}{z}, r32 VPBROADCASTB zmm {k}{z}, r32
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
r32explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-6
VPBROADCASTB xmm {k}{z}, xmm/m8 VPBROADCASTB ymm {k}{z}, xmm/m8 VPBROADCASTB zmm {k}{z}, xmm/m8
AVX512-E6
VPBROADCASTB xmm {k}{z}, r32 VPBROADCASTB ymm {k}{z}, r32 VPBROADCASTB zmm {k}{z}, r32
AVX512-E7NM

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_broadcastb_epi8 __m128i _mm_broadcastb_epi8(__m128i __X)

VPBROADCASTB xmm, xmm VEX.128 -mavx2

_mm_mask_broadcastb_epi8 __m128i _mm_mask_broadcastb_epi8(__m128i __O, __mmask16 __M, __m128i __A)

VPBROADCASTB xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_mask_set1_epi8 __m128i _mm_mask_set1_epi8(__m128i __O, __mmask16 __M, char __A)

VPBROADCASTB xmm {k}, r32 EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_broadcastb_epi8 __m128i _mm_maskz_broadcastb_epi8(__mmask16 __M, __m128i __A)

VPBROADCASTB xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_set1_epi8 __m128i _mm_maskz_set1_epi8(__mmask16 __M, char __A)

VPBROADCASTB xmm {k}{z}, r32 EVEX.128 -mavx512vl -mavx512bw

_mm256_broadcastb_epi8 __m256i _mm256_broadcastb_epi8(__m128i __X)

VPBROADCASTB ymm, xmm VEX.256 -mavx2

_mm256_mask_broadcastb_epi8 __m256i _mm256_mask_broadcastb_epi8(__m256i __O, __mmask32 __M, __m128i __A)

VPBROADCASTB ymm {k}, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_set1_epi8 __m256i _mm256_mask_set1_epi8(__m256i __O, __mmask32 __M, char __A)

VPBROADCASTB ymm {k}, r32 EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_broadcastb_epi8 __m256i _mm256_maskz_broadcastb_epi8(__mmask32 __M, __m128i __A)

VPBROADCASTB ymm {k}{z}, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_set1_epi8 __m256i _mm256_maskz_set1_epi8(__mmask32 __M, char __A)

VPBROADCASTB ymm {k}{z}, r32 EVEX.256 -mavx512vl -mavx512bw

_mm512_broadcastb_epi8 __m512i _mm512_broadcastb_epi8(__m128i __A)

VPBROADCASTB zmm, xmm EVEX.512 -mavx512bw

_mm512_mask_broadcastb_epi8 __m512i _mm512_mask_broadcastb_epi8(__m512i __O, __mmask64 __M, __m128i __A)

VPBROADCASTB zmm {k}, xmm EVEX.512 -mavx512bw

_mm512_mask_set1_epi8 __m512i _mm512_mask_set1_epi8(__m512i __O, __mmask64 __M, char __A)

VPBROADCASTB zmm {k}, r32 EVEX.512 -mavx512bw

_mm512_maskz_broadcastb_epi8 __m512i _mm512_maskz_broadcastb_epi8(__mmask64 __M, __m128i __A)

VPBROADCASTB zmm {k}{z}, xmm EVEX.512 -mavx512bw

_mm512_maskz_set1_epi8 __m512i _mm512_maskz_set1_epi8(__mmask64 __M, char __A)

VPBROADCASTB zmm {k}{z}, r32 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-442 (VPBROADCAST); Volume 2C, page 5-451 (VPBROADCASTB/W/D/Q)
  6. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.