Extensions
Forms
13 (4 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

VPBROADCASTD fills every doubleword of a vector with one value: the low doubleword of an XMM register, a doubleword in memory, or, in the EVEX forms, a general-purpose register. Vector code uses it to set up a constant or a loop-invariant value in every element, which is what _mm256_set1_epi32(x) asks for.

The sources differ by encoding:

  • VEX (AVX2) takes an XMM register or memory. A value in a general-purpose register first goes to an XMM register: GCC 14 and Clang 23 at -O2 compile _mm256_set1_epi32(x) to VMOVD and VPBROADCASTD. AVX itself could broadcast only from memory, with VBROADCASTSS, which copies the same 32 bits; for AVX2, Clang emits that instruction for a broadcast of an integer from memory.
  • EVEX (AVX-512F) adds the general-purpose register source (opcode 7C) and masking, so with AVX-512 both compilers broadcast straight from the register.

The memory form reads only the four bytes of the value, at any alignment, so it never touches the bytes around it. That makes it a compact way to load a repeated constant: a 4-byte literal instead of a 32- or 64-byte one, which is how Clang loads such constants with AVX2. With AVX-512 Clang goes further and uses embedded broadcast, a memory operand marked {1to8} or {1to16} that the arithmetic instruction itself repeats across the vector, with no VPBROADCASTD at all. GCC 14 instead builds the constant in a general-purpose register and broadcasts it from there.

VPBROADCASTB, VPBROADCASTW and VPBROADCASTQ do the same for other element sizes, VBROADCASTI128 repeats 16 bytes, and VPBROADCASTMW2D copies a mask register into every element.

In the optimization guide

What the optimization guide says about VPBROADCASTD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Skylake to Cooper Lake

  • AVX-512 and frequency on the servers: A broadcast of a 32-bit or 64-bit element from memory runs on the load ports, sparing port 5; a 16-bit one still goes through port 5, so it gains nothing from the memory form.

Forms

Every encoding of VPBROADCASTD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPBROADCASTD xmm, m32 VPBROADCASTD_XMMdq_MEMdVEX.128.66.0F38.W0 58 /rAVX2
VPBROADCASTD xmm, xmm VPBROADCASTD_XMMdq_XMMdVEX.128.66.0F38.W0 58 /rAVX2
VPBROADCASTD ymm, m32 VPBROADCASTD_YMMqq_MEMdVEX.256.66.0F38.W0 58 /rAVX2
VPBROADCASTD ymm, xmm VPBROADCASTD_YMMqq_XMMdVEX.256.66.0F38.W0 58 /rAVX2
VPBROADCASTD zmm {k}{z}, m32 VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512EVEX.512.66.0F38.W0 58 /rAVX10.1 or AVX512F
VPBROADCASTD zmm {k}{z}, xmm VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512EVEX.512.66.0F38.W0 58 /rAVX10.1 or AVX512F
VPBROADCASTD zmm {k}{z}, r32 VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512EVEX.512.66.0F38.W0 7C /rAVX10.1 or AVX512F
VPBROADCASTD xmm {k}{z}, m32 VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512EVEX.128.66.0F38.W0 58 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTD xmm {k}{z}, xmm VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512EVEX.128.66.0F38.W0 58 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTD xmm {k}{z}, r32 VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512EVEX.128.66.0F38.W0 7C /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTD ymm {k}{z}, m32 VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512EVEX.256.66.0F38.W0 58 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTD ymm {k}{z}, xmm VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512EVEX.256.66.0F38.W0 58 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTD ymm {k}{z}, r32 VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512EVEX.256.66.0F38.W0 7C /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m32xmm, xmm
xmm {k}{z}, xmm
ymm, m32ymm, xmm
zmm {k}{z}, xmm
ymm {k}{z}, xmm
zmm {k}{z}, m32no mask
ymm {k}{z}, m32no mask
zmm {k}{z}, m32with a mask, zeroingzmm {k}{z}, r32
ymm {k}{z}, r32
xmm {k}{z}, m32no maskxmm {k}{z}, m32with a mask, zeroingxmm {k}{z}, r32ymm {k}{z}, m32with a mask, zeroing
Haswell, Skylake6 / 0.5p231 / 1p57 / 0.5p233 / 1p5
Broadwell5 / 0.5p231 / 1p56 / 0.5p233 / 1p5
Skylake-SP, Ice Lake6 / 0.5p231 / 1p57 / 0.5p233 / 1p58 / 0.5p0158 / 0.5p0153 / 1p57 / 0.5p0157 / 0.5p0151 / 1p58 / 0.5p015
Alder Lake7 / 0.33p2 p3 p101 / 1p58 / 0.33p2 p3 p103 / 1p5
Sapphire Rapids7 / 0.33p2 p3 p101 / 1p58 / 0.33p2 p3 p103 / 1p58 / 0.33p2 p3 p109 / 0.5p055 / 1p57 / 0.33p2 p3 p108 / 0.33p0155 / 1p59 / 0.33p015
Lunar Lake6 / 2p20 p21 p221 / 0.33p1357 / 2.33p20 p21 p223 / 0.5V2 V3
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU22 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU22 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP1
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 11FP18 / 1FP18 / 1FP11 / 1FP18 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.52FP1 FP28 / 1FP1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2014; AMD 58455, row 1299).
  2. Zen 4 model: AMD's spreadsheets give reciprocal throughput 1 for Zen 4 and Zen 5 (AMD 57647, row 2007; AMD 58455, row 514).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: the low doubleword goes to every doubleword of the result.
VPBROADCASTD: one doubleword everywhereResult doublewords 15 to 0: a0, unchanged (bit 14 of k1 is 0), a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.0123xmm2or r32, m32a1111111111111110k1a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0zmm1

Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 doublewords. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doublewords 15 to 0: a0, unchanged (bit 14 of k1 is 0), a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[0]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 13 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPBROADCASTD xmm, xmm/m32 VPBROADCASTD ymm, xmm/m32
xmm, ymmexplicitwrite
xmm/m32explicitread
VPBROADCASTD xmm {k}{z}, xmm/m32 VPBROADCASTD ymm {k}{z}, xmm/m32 VPBROADCASTD zmm {k}{z}, xmm/m32
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m32explicitread
VPBROADCASTD xmm {k}{z}, r32 VPBROADCASTD ymm {k}{z}, r32 VPBROADCASTD zmm {k}{z}, r32
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
r32explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-6
VPBROADCASTD xmm {k}{z}, xmm/m32 VPBROADCASTD ymm {k}{z}, xmm/m32 VPBROADCASTD zmm {k}{z}, xmm/m32
AVX512-E6
VPBROADCASTD xmm {k}{z}, r32 VPBROADCASTD ymm {k}{z}, r32 VPBROADCASTD zmm {k}{z}, r32
AVX512-E7NM

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_broadcastd_epi32 __m128i _mm_broadcastd_epi32(__m128i __X)

VPBROADCASTD xmm, xmm VEX.128 -mavx2

_mm_broadcastmw_epi32 __m128i _mm_broadcastmw_epi32(__mmask16 __A)

VPBROADCASTD xmm, r32 EVEX.128 -mavx512vl -mavx512cd

_mm_mask_broadcastd_epi32 __m128i _mm_mask_broadcastd_epi32(__m128i __O, __mmask8 __M, __m128i __A)

VPBROADCASTD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_set1_epi32 __m128i _mm_mask_set1_epi32(__m128i __O, __mmask8 __M, int __A)

VPBROADCASTD xmm {k}, r32 EVEX.128 -mavx512vl

_mm_maskz_broadcastd_epi32 __m128i _mm_maskz_broadcastd_epi32(__mmask8 __M, __m128i __A)

VPBROADCASTD xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm_maskz_set1_epi32 __m128i _mm_maskz_set1_epi32(__mmask8 __M, int __A)

VPBROADCASTD xmm {k}{z}, r32 EVEX.128 -mavx512vl

_mm256_broadcastd_epi32 __m256i _mm256_broadcastd_epi32(__m128i __X)

VPBROADCASTD ymm, xmm VEX.256 -mavx2

_mm256_broadcastmw_epi32 __m256i _mm256_broadcastmw_epi32(__mmask16 __A)

VPBROADCASTD ymm, r32 EVEX.256 -mavx512vl -mavx512cd

_mm256_mask_broadcastd_epi32 __m256i _mm256_mask_broadcastd_epi32(__m256i __O, __mmask8 __M, __m128i __A)

VPBROADCASTD ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_mask_set1_epi32 __m256i _mm256_mask_set1_epi32(__m256i __O, __mmask8 __M, int __A)

VPBROADCASTD ymm {k}, r32 EVEX.256 -mavx512vl

_mm256_maskz_broadcastd_epi32 __m256i _mm256_maskz_broadcastd_epi32(__mmask8 __M, __m128i __A)

VPBROADCASTD ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm256_maskz_set1_epi32 __m256i _mm256_maskz_set1_epi32(__mmask8 __M, int __A)

VPBROADCASTD ymm {k}{z}, r32 EVEX.256 -mavx512vl

_mm512_broadcastd_epi32 __m512i _mm512_broadcastd_epi32(__m128i __A)

VPBROADCASTD zmm, xmm EVEX.512 -mavx512f

_mm512_broadcastmw_epi32 __m512i _mm512_broadcastmw_epi32(__mmask16 __A)

VPBROADCASTD zmm, r32 EVEX.512 -mavx512cd

_mm512_set1_epi32 __m512i _mm512_set1_epi32(int __s)

VPBROADCASTD zmm, r32 EVEX.512 -mavx512f

_mm512_mask_broadcastd_epi32 __m512i _mm512_mask_broadcastd_epi32(__m512i __O, __mmask16 __M, __m128i __A)

VPBROADCASTD zmm {k}, xmm EVEX.512 -mavx512f

_mm512_mask_set1_epi32 __m512i _mm512_mask_set1_epi32(__m512i __O, __mmask16 __M, int __A)

VPBROADCASTD zmm {k}, r32 EVEX.512 -mavx512f

_mm512_maskz_broadcastd_epi32 __m512i _mm512_maskz_broadcastd_epi32(__mmask16 __M, __m128i __A)

VPBROADCASTD zmm {k}{z}, xmm EVEX.512 -mavx512f

_mm512_maskz_set1_epi32 __m512i _mm512_maskz_set1_epi32(__mmask16 __M, int __A)

VPBROADCASTD zmm {k}{z}, r32 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-442 (VPBROADCAST); Volume 2C, page 5-451 (VPBROADCASTB/W/D/Q)
  6. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.