Instruction
VPBROADCASTD
Copies one doubleword from a register or memory to every doubleword of a vector.
VPBROADCASTD fills every doubleword of a vector with one value: the low
doubleword of an XMM register, a doubleword in memory, or, in the EVEX
forms, a general-purpose register. Vector code uses it to set up a
constant or a loop-invariant value in every element, which is what
_mm256_set1_epi32(x) asks for.
The sources differ by encoding:
- VEX (AVX2) takes an XMM register or memory. A value in a
general-purpose register first goes to an XMM register: GCC 14 and
Clang 23 at -O2 compile
_mm256_set1_epi32(x)to VMOVD and VPBROADCASTD. AVX itself could broadcast only from memory, with VBROADCASTSS, which copies the same 32 bits; for AVX2, Clang emits that instruction for a broadcast of an integer from memory. - EVEX (AVX-512F) adds the general-purpose register source (opcode 7C) and masking, so with AVX-512 both compilers broadcast straight from the register.
The memory form reads only the four bytes of the value, at any
alignment, so it never touches the bytes around it. That makes it a
compact way to load a repeated constant: a 4-byte literal instead of a
32- or 64-byte one, which is how Clang loads such constants with AVX2.
With AVX-512 Clang goes further and uses embedded broadcast, a memory
operand marked {1to8} or {1to16} that the arithmetic instruction
itself repeats across the vector, with no VPBROADCASTD at all. GCC 14
instead builds the constant in a general-purpose register and broadcasts
it from there.
VPBROADCASTB, VPBROADCASTW and VPBROADCASTQ do the same for other element sizes, VBROADCASTI128 repeats 16 bytes, and VPBROADCASTMW2D copies a mask register into every element.
In the optimization guide
What the optimization guide says about VPBROADCASTD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.
Skylake to Cooper Lake
- AVX-512 and frequency on the servers: A broadcast of a 32-bit or 64-bit element from memory runs on the load ports, sparing port 5; a 16-bit one still goes through port 5, so it gains nothing from the memory form.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPBROADCASTD xmm, m32
VPBROADCASTD_XMMdq_MEMd | VEX.128.66.0F38.W0 58 /r | AVX2 |
VPBROADCASTD xmm, xmm
VPBROADCASTD_XMMdq_XMMd | VEX.128.66.0F38.W0 58 /r | AVX2 |
VPBROADCASTD ymm, m32
VPBROADCASTD_YMMqq_MEMd | VEX.256.66.0F38.W0 58 /r | AVX2 |
VPBROADCASTD ymm, xmm
VPBROADCASTD_YMMqq_XMMd | VEX.256.66.0F38.W0 58 /r | AVX2 |
VPBROADCASTD zmm {k}{z}, m32
VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 | EVEX.512.66.0F38.W0 58 /r | AVX10.1 or AVX512F |
VPBROADCASTD zmm {k}{z}, xmm
VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 | EVEX.512.66.0F38.W0 58 /r | AVX10.1 or AVX512F |
VPBROADCASTD zmm {k}{z}, r32
VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 | EVEX.512.66.0F38.W0 7C /r | AVX10.1 or AVX512F |
VPBROADCASTD xmm {k}{z}, m32
VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 | EVEX.128.66.0F38.W0 58 /r | AVX10.1 or AVX512F + AVX512VL |
VPBROADCASTD xmm {k}{z}, xmm
VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 | EVEX.128.66.0F38.W0 58 /r | AVX10.1 or AVX512F + AVX512VL |
VPBROADCASTD xmm {k}{z}, r32
VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 | EVEX.128.66.0F38.W0 7C /r | AVX10.1 or AVX512F + AVX512VL |
VPBROADCASTD ymm {k}{z}, m32
VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 | EVEX.256.66.0F38.W0 58 /r | AVX10.1 or AVX512F + AVX512VL |
VPBROADCASTD ymm {k}{z}, xmm
VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 | EVEX.256.66.0F38.W0 58 /r | AVX10.1 or AVX512F + AVX512VL |
VPBROADCASTD ymm {k}{z}, r32
VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 | EVEX.256.66.0F38.W0 7C /r | AVX10.1 or AVX512F + AVX512VL |
Latency and throughput
| Model | xmm, m32 | xmm, xmmxmm {k}{z}, xmm | ymm, m32 | ymm, xmmzmm {k}{z}, xmmymm {k}{z}, xmm | zmm {k}{z}, m32no maskymm {k}{z}, m32no mask | zmm {k}{z}, m32with a mask, zeroing | zmm {k}{z}, r32ymm {k}{z}, r32 | xmm {k}{z}, m32no mask | xmm {k}{z}, m32with a mask, zeroing | xmm {k}{z}, r32 | ymm {k}{z}, m32with a mask, zeroing |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Haswell, Skylake | 6 / 0.5p23 | 1 / 1p5 | 7 / 0.5p23 | 3 / 1p5 | |||||||
| Broadwell | 5 / 0.5p23 | 1 / 1p5 | 6 / 0.5p23 | 3 / 1p5 | |||||||
| Skylake-SP, Ice Lake | 6 / 0.5p23 | 1 / 1p5 | 7 / 0.5p23 | 3 / 1p5 | 8 / 0.5p015 | 8 / 0.5p015 | 3 / 1p5 | 7 / 0.5p015 | 7 / 0.5p015 | 1 / 1p5 | 8 / 0.5p015 |
| Alder Lake | 7 / 0.33p2 p3 p10 | 1 / 1p5 | 8 / 0.33p2 p3 p10 | 3 / 1p5 | |||||||
| Sapphire Rapids | 7 / 0.33p2 p3 p10 | 1 / 1p5 | 8 / 0.33p2 p3 p10 | 3 / 1p5 | 8 / 0.33p2 p3 p10 | 9 / 0.5p05 | 5 / 1p5 | 7 / 0.33p2 p3 p10 | 8 / 0.33p015 | 5 / 1p5 | 9 / 0.33p015 |
| Lunar Lake | 6 / 2p20 p21 p22 | 1 / 0.33p135 | 7 / 2.33p20 p21 p22 | 3 / 0.5V2 V3 | |||||||
| Zen | 8 / 0.5FPU1 FPU2 | 1 / 0.5FPU1 FPU2 | 8 / 0.5FPU1 FPU2 | 2 / 1FPU1 FPU2 | |||||||
| Zen 2 | 8 / 0.5FPU1 FPU2 | 1 / 0.5FPU1 FPU2 | 8 / 0.5FPU1 FPU2 | 2 / 0.5FPU1 FPU2 | |||||||
| Zen 3 | 8 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 2 / 1FP1 | |||||||
| Zen 4 | 8 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 1 / 11FP1 | 8 / 1FP1 | 8 / 1FP1 | 1 / 1FP1 | 8 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 1 / 0.52FP1 FP2 | 8 / 1FP1 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 doublewords. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result doublewords 15 to 0: a0, unchanged (bit 14 of k1 is 0), a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 32):
if k1[i]: # 1 without a write mask
zmm1.d[i] = src2.d[0]
elif zeroing:
zmm1.d[i] = 0
# else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 13 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPBROADCASTD xmm, xmm/m32 VPBROADCASTD ymm, xmm/m32 | ||
xmm, ymm | explicit | write |
xmm/m32 | explicit | read |
VPBROADCASTD xmm {k}{z}, xmm/m32 VPBROADCASTD ymm {k}{z}, xmm/m32 VPBROADCASTD zmm {k}{z}, xmm/m32 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m32 | explicit | read |
VPBROADCASTD xmm {k}{z}, r32 VPBROADCASTD ymm {k}{z}, r32 VPBROADCASTD zmm {k}{z}, r32 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
r32 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- VEX forms
avx-type-6VPBROADCASTD xmm {k}{z}, xmm/m32VPBROADCASTD ymm {k}{z}, xmm/m32VPBROADCASTD zmm {k}{z}, xmm/m32AVX512-E6VPBROADCASTD xmm {k}{z}, r32VPBROADCASTD ymm {k}{z}, r32VPBROADCASTD zmm {k}{z}, r32AVX512-E7NM
Attributes
What else XED records about the forms. How to read.
- EVEX forms
- write masking
- EVEX memory forms
- memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_broadcastd_epi32
__m128i _mm_broadcastd_epi32(__m128i __X) |
|
_mm_broadcastmw_epi32
__m128i _mm_broadcastmw_epi32(__mmask16 __A) |
|
_mm_mask_broadcastd_epi32
__m128i _mm_mask_broadcastd_epi32(__m128i __O, __mmask8 __M, __m128i __A) |
|
_mm_mask_set1_epi32
__m128i _mm_mask_set1_epi32(__m128i __O, __mmask8 __M, int __A) |
|
_mm_maskz_broadcastd_epi32
__m128i _mm_maskz_broadcastd_epi32(__mmask8 __M, __m128i __A) |
|
_mm_maskz_set1_epi32
__m128i _mm_maskz_set1_epi32(__mmask8 __M, int __A) |
|
_mm256_broadcastd_epi32
__m256i _mm256_broadcastd_epi32(__m128i __X) |
|
_mm256_broadcastmw_epi32
__m256i _mm256_broadcastmw_epi32(__mmask16 __A) |
|
_mm256_mask_broadcastd_epi32
__m256i _mm256_mask_broadcastd_epi32(__m256i __O, __mmask8 __M, __m128i __A) |
|
_mm256_mask_set1_epi32
__m256i _mm256_mask_set1_epi32(__m256i __O, __mmask8 __M, int __A) |
|
_mm256_maskz_broadcastd_epi32
__m256i _mm256_maskz_broadcastd_epi32(__mmask8 __M, __m128i __A) |
|
_mm256_maskz_set1_epi32
__m256i _mm256_maskz_set1_epi32(__mmask8 __M, int __A) |
|
_mm512_broadcastd_epi32
__m512i _mm512_broadcastd_epi32(__m128i __A) |
|
_mm512_broadcastmw_epi32
__m512i _mm512_broadcastmw_epi32(__mmask16 __A) |
|
_mm512_set1_epi32
__m512i _mm512_set1_epi32(int __s) |
|
_mm512_mask_broadcastd_epi32
__m512i _mm512_mask_broadcastd_epi32(__m512i __O, __mmask16 __M, __m128i __A) |
|
_mm512_mask_set1_epi32
__m512i _mm512_mask_set1_epi32(__m512i __O, __mmask16 __M, int __A) |
|
_mm512_maskz_broadcastd_epi32
__m512i _mm512_maskz_broadcastd_epi32(__mmask16 __M, __m128i __A) |
|
_mm512_maskz_set1_epi32
__m512i _mm512_maskz_set1_epi32(__mmask16 __M, int __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More AVX2 instructions
- VPACKSSWB
- VPACKUSDW
- VPACKUSWB
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDD
- VPBLENDVB
- VPBLENDW
- VPBROADCASTB
- VPBROADCASTQ
- VPBROADCASTW
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPERM2I128
- VPERMD
- VPERMPD
- VPERMPS
- VPERMQ
- VPGATHERDD
- VPGATHERDQ
- VPGATHERQD
- VPGATHERQQ
- VPHADDD
More AVX10.1 instructions
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPANDD
- VPANDND
- VPANDNQ
- VPANDQ
- VPAVGB
- VPAVGW
- VPBLENDMB
- VPBLENDMD
- VPBLENDMQ
- VPBLENDMW
- VPBROADCASTB
- VPBROADCASTMB2Q
- VPBROADCASTMW2D
- VPBROADCASTQ
- VPBROADCASTW
- VPCLMULQDQ
- VPCMPB
- VPCMPD
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPQ
- VPCMPUB
- VPCMPUD
- VPCMPUQ
- VPCMPUW
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-442 (VPBROADCAST); Volume 2C, page 5-451 (VPBROADCASTB/
W/ D/ Q) - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.