VPBROADCASTMW2D instruction (AVX10.1)

VPBROADCASTMW2D copies the low 16 bits of a mask register, zero-extended to 32, into every doubleword of a vector register; bits 63:16 of the mask are ignored. It is the doubleword sibling of VPBROADCASTMB2Q, whose page explains what the pair is for and how it differs from VPMOVM2D, which spreads one bit to each element instead. Sixteen bits are one per doubleword of a ZMM register, the elements of VPCONFLICTD: ANDing its result with the broadcast mask keeps only the conflicts with the elements that the mask selects. It belongs to AVX512CD, takes no write mask, and has XMM and YMM forms under AVX512VL.

Recorded on Zen 5

The low 16 bits only. From a K3 of 84F67CBF556B1758h, vpbroadcastmw2d zmm0, k3 wrote 00001758h into all sixteen doublewords.
Narrow forms clear above. The XMM form wrote 00005307h four times from K6 and the YMM form 00002D83h eight times from K4, and both cleared the register above them, up to bit 511.

In compiled code

_mm512_broadcastmw_epi32 takes its mask as an argument, which arrives in a general register: at -O2 with -march=x86-64-v4, GCC 14 moves it into a mask register with KMOVW and emits VPBROADCASTMW2D, while Clang 23 broadcasts the general register with VPBROADCASTD. For the mask of a compare, _mm512_set1_epi32(_mm512_cmpeq_epi32_mask(a, b)), it is the other way round: Clang emits VPBROADCASTMW2D straight from the mask register, GCC a KMOVD to EAX and VPBROADCASTD.

AMD’s Zen 5 latency spreadsheet gives one macro-op with a latency of 2 cycles on pipe FP1 or FP2, as for VPBROADCASTMB2Q.

Forms

Every encoding of VPBROADCASTMW2D that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPBROADCASTMW2D zmm, k` VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD	`EVEX.512.F3.0F38.W0 3A /r`	AVX10.1 or AVX512CD
`VPBROADCASTMW2D xmm, k` VPBROADCASTMW2D_XMMu32_MASKu32_AVX512	`EVEX.128.F3.0F38.W0 3A /r`	AVX10.1 or AVX512CD + AVX512VL
`VPBROADCASTMW2D ymm, k` VPBROADCASTMW2D_YMMu32_MASKu32_AVX512	`EVEX.256.F3.0F38.W0 3A /r`	AVX10.1 or AVX512CD + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`zmm, k` `xmm, k` `ymm, k`
Skylake-SP, Ice Lake	1 / 1p5
Sapphire Rapids	6 / 1p05
Zen 4	1 / 0.5FP1 FP2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Broadcast: the low 16 bits of k2, zero-extended, goes to every doubleword of the result.

Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 doublewords.

Result doublewords 15 to 0: a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = k2.read() & 0xFFFF  # the low 16 bits
for i in range(VL // 32):
    zmm1.d[i] = x
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPBROADCASTMW2D xmm, k` `VPBROADCASTMW2D ymm, k` `VPBROADCASTMW2D zmm, k`
`xmm, ymm, zmm`	explicit	write
`k`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E6NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512CD_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512CD `CPUID.(EAX=07H,ECX=0):EBX[28]` AVX512CD	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
`AVX512CD_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512CD + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[28]` AVX512CD `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512CD_256` AVX10.1	Same as `AVX512CD_128`	Same as `AVX512CD_128`

AVX512CD_512