x86-64.net

Instruction

VPBROADCASTQ

Copies one quadword from a register or memory to every quadword of a vector.

Extensions
Forms
13 (4 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPBROADCASTQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPBROADCASTQ xmm, m64 VPBROADCASTQ_XMMdq_MEMqVEX.128.66.0F38.W0 59 /rAVX2
VPBROADCASTQ xmm, xmm VPBROADCASTQ_XMMdq_XMMqVEX.128.66.0F38.W0 59 /rAVX2
VPBROADCASTQ ymm, m64 VPBROADCASTQ_YMMqq_MEMqVEX.256.66.0F38.W0 59 /rAVX2
VPBROADCASTQ ymm, xmm VPBROADCASTQ_YMMqq_XMMqVEX.256.66.0F38.W0 59 /rAVX2
VPBROADCASTQ zmm {k}{z}, m64 VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512EVEX.512.66.0F38.W1 59 /rAVX10.1 or AVX512F
VPBROADCASTQ zmm {k}{z}, xmm VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512EVEX.512.66.0F38.W1 59 /rAVX10.1 or AVX512F
VPBROADCASTQ zmm {k}{z}, r64 64-bit mode only VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512EVEX.512.66.0F38.W1 7C /rAVX10.1 or AVX512F
VPBROADCASTQ xmm {k}{z}, m64 VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512EVEX.128.66.0F38.W1 59 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTQ xmm {k}{z}, xmm VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512EVEX.128.66.0F38.W1 59 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTQ xmm {k}{z}, r64 64-bit mode only VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512EVEX.128.66.0F38.W1 7C /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTQ ymm {k}{z}, m64 VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512EVEX.256.66.0F38.W1 59 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTQ ymm {k}{z}, xmm VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512EVEX.256.66.0F38.W1 59 /rAVX10.1 or AVX512F + AVX512VL
VPBROADCASTQ ymm {k}{z}, r64 64-bit mode only VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512EVEX.256.66.0F38.W1 7C /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_broadcast_i32x2 __m128i _mm_broadcast_i32x2(__m128i __A)

VPBROADCASTQ xmm, xmm VEX.128 -mavx512vl -mavx512dq

_mm_broadcastmb_epi64 __m128i _mm_broadcastmb_epi64(__mmask8 __A)

VPBROADCASTQ xmm, r64 EVEX.128 -mavx512vl -mavx512cd

_mm_broadcastq_epi64 __m128i _mm_broadcastq_epi64(__m128i __X)

VPBROADCASTQ xmm, xmm VEX.128 -mavx2

_mm_mask_broadcastq_epi64 __m128i _mm_mask_broadcastq_epi64(__m128i __O, __mmask8 __M, __m128i __A)

VPBROADCASTQ xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_set1_epi64 __m128i _mm_mask_set1_epi64(__m128i __O, __mmask8 __M, long long __A)

VPBROADCASTQ xmm {k}, r64 EVEX.128 -mavx512vl

_mm_maskz_broadcastq_epi64 __m128i _mm_maskz_broadcastq_epi64(__mmask8 __M, __m128i __A)

VPBROADCASTQ xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm_maskz_set1_epi64 __m128i _mm_maskz_set1_epi64(__mmask8 __M, long long __A)

VPBROADCASTQ xmm {k}{z}, r64 EVEX.128 -mavx512vl

_mm256_broadcast_i32x2 __m256i _mm256_broadcast_i32x2(__m128i __A)

VPBROADCASTQ ymm, xmm VEX.256 -mavx512vl -mavx512dq

_mm256_broadcastmb_epi64 __m256i _mm256_broadcastmb_epi64(__mmask8 __A)

VPBROADCASTQ ymm, r64 EVEX.256 -mavx512vl -mavx512cd

_mm256_broadcastq_epi64 __m256i _mm256_broadcastq_epi64(__m128i __X)

VPBROADCASTQ ymm, xmm VEX.256 -mavx2

_mm256_mask_broadcastq_epi64 __m256i _mm256_mask_broadcastq_epi64(__m256i __O, __mmask8 __M, __m128i __A)

VPBROADCASTQ ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_mask_set1_epi64 __m256i _mm256_mask_set1_epi64(__m256i __O, __mmask8 __M, long long __A)

VPBROADCASTQ ymm {k}, r64 EVEX.256 -mavx512vl

_mm256_maskz_broadcastq_epi64 __m256i _mm256_maskz_broadcastq_epi64(__mmask8 __M, __m128i __A)

VPBROADCASTQ ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm256_maskz_set1_epi64 __m256i _mm256_maskz_set1_epi64(__mmask8 __M, long long __A)

VPBROADCASTQ ymm {k}{z}, r64 EVEX.256 -mavx512vl

_mm512_broadcastmb_epi64 __m512i _mm512_broadcastmb_epi64(__mmask8 __A)

VPBROADCASTQ zmm, r64 EVEX.512 -mavx512cd

_mm512_broadcastq_epi64 __m512i _mm512_broadcastq_epi64(__m128i __A)

VPBROADCASTQ zmm, xmm EVEX.512 -mavx512f

_mm512_set1_epi64 __m512i _mm512_set1_epi64(long long __d)

VPBROADCASTQ zmm, r64 EVEX.512 -mavx512f

_mm512_mask_broadcastq_epi64 __m512i _mm512_mask_broadcastq_epi64(__m512i __O, __mmask8 __M, __m128i __A)

VPBROADCASTQ zmm {k}, xmm EVEX.512 -mavx512f

_mm512_mask_set1_epi64 __m512i _mm512_mask_set1_epi64(__m512i __O, __mmask8 __M, long long __A)

VPBROADCASTQ zmm {k}, r64 EVEX.512 -mavx512f

_mm512_maskz_broadcastq_epi64 __m512i _mm512_maskz_broadcastq_epi64(__mmask8 __M, __m128i __A)

VPBROADCASTQ zmm {k}{z}, xmm EVEX.512 -mavx512f

_mm512_maskz_set1_epi64 __m512i _mm512_maskz_set1_epi64(__mmask8 __M, long long __A)

VPBROADCASTQ zmm {k}{z}, r64 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.