x86-64.net

Instruction

VPBROADCASTW

Copies one word from a register or memory to every word of a vector.

Extensions
Forms
13 (4 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPBROADCASTW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPBROADCASTW xmm, m16 VPBROADCASTW_XMMdq_MEMwVEX.128.66.0F38.W0 79 /rAVX2
VPBROADCASTW xmm, xmm VPBROADCASTW_XMMdq_XMMwVEX.128.66.0F38.W0 79 /rAVX2
VPBROADCASTW ymm, m16 VPBROADCASTW_YMMqq_MEMwVEX.256.66.0F38.W0 79 /rAVX2
VPBROADCASTW ymm, xmm VPBROADCASTW_YMMqq_XMMwVEX.256.66.0F38.W0 79 /rAVX2
VPBROADCASTW xmm {k}{z}, xmm VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512EVEX.128.66.0F38.W0 79 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTW xmm {k}{z}, m16 VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512EVEX.128.66.0F38.W0 79 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTW xmm {k}{z}, r32 VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512EVEX.128.66.0F38.W0 7B /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTW ymm {k}{z}, xmm VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512EVEX.256.66.0F38.W0 79 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTW ymm {k}{z}, m16 VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512EVEX.256.66.0F38.W0 79 /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTW ymm {k}{z}, r32 VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512EVEX.256.66.0F38.W0 7B /rAVX10.1 or AVX512BW + AVX512VL
VPBROADCASTW zmm {k}{z}, xmm VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512EVEX.512.66.0F38.W0 79 /rAVX10.1 or AVX512BW
VPBROADCASTW zmm {k}{z}, m16 VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512EVEX.512.66.0F38.W0 79 /rAVX10.1 or AVX512BW
VPBROADCASTW zmm {k}{z}, r32 VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512EVEX.512.66.0F38.W0 7B /rAVX10.1 or AVX512BW

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_broadcastw_epi16 __m128i _mm_broadcastw_epi16(__m128i __X)

VPBROADCASTW xmm, xmm VEX.128 -mavx2

_mm_set1_pbh __m128bh _mm_set1_pbh(__bf16 bf)

VPBROADCASTW xmm, xmm VEX.128 -mavx10.2

_mm_set1_ph __m128h _mm_set1_ph(_Float16 __h)

VPBROADCASTW xmm, xmm VEX.128 -mavx512fp16 -mavx512vl

_mm_mask_broadcastw_epi16 __m128i _mm_mask_broadcastw_epi16(__m128i __O, __mmask8 __M, __m128i __A)

VPBROADCASTW xmm {k}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_mask_set1_epi16 __m128i _mm_mask_set1_epi16(__m128i __O, __mmask8 __M, short __A)

VPBROADCASTW xmm {k}, r32 EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_broadcastw_epi16 __m128i _mm_maskz_broadcastw_epi16(__mmask8 __M, __m128i __A)

VPBROADCASTW xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_set1_epi16 __m128i _mm_maskz_set1_epi16(__mmask8 __M, short __A)

VPBROADCASTW xmm {k}{z}, r32 EVEX.128 -mavx512vl -mavx512bw

_mm256_broadcastw_epi16 __m256i _mm256_broadcastw_epi16(__m128i __X)

VPBROADCASTW ymm, xmm VEX.256 -mavx2

_mm256_set1_pbh __m256bh _mm256_set1_pbh(__bf16 bf)

VPBROADCASTW ymm, xmm VEX.256 -mavx10.2

_mm256_set1_ph __m256h _mm256_set1_ph(_Float16 __h)

VPBROADCASTW ymm, xmm VEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_broadcastw_epi16 __m256i _mm256_mask_broadcastw_epi16(__m256i __O, __mmask16 __M, __m128i __A)

VPBROADCASTW ymm {k}, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_set1_epi16 __m256i _mm256_mask_set1_epi16(__m256i __O, __mmask16 __M, short __A)

VPBROADCASTW ymm {k}, r32 EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_broadcastw_epi16 __m256i _mm256_maskz_broadcastw_epi16(__mmask16 __M, __m128i __A)

VPBROADCASTW ymm {k}{z}, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_set1_epi16 __m256i _mm256_maskz_set1_epi16(__mmask16 __M, short __A)

VPBROADCASTW ymm {k}{z}, r32 EVEX.256 -mavx512vl -mavx512bw

_mm512_broadcastw_epi16 __m512i _mm512_broadcastw_epi16(__m128i __A)

VPBROADCASTW zmm, xmm EVEX.512 -mavx512bw

_mm512_set1_pbh __m512bh _mm512_set1_pbh(__bf16 bf)

VPBROADCASTW zmm, xmm EVEX.512 -mavx10.2

_mm512_set1_ph __m512h _mm512_set1_ph(_Float16 __h)

VPBROADCASTW zmm, xmm EVEX.512 -mavx512fp16

_mm512_mask_broadcastw_epi16 __m512i _mm512_mask_broadcastw_epi16(__m512i __O, __mmask32 __M, __m128i __A)

VPBROADCASTW zmm {k}, xmm EVEX.512 -mavx512bw

_mm512_mask_set1_epi16 __m512i _mm512_mask_set1_epi16(__m512i __O, __mmask32 __M, short __A)

VPBROADCASTW zmm {k}, r32 EVEX.512 -mavx512bw

_mm512_maskz_broadcastw_epi16 __m512i _mm512_maskz_broadcastw_epi16(__mmask32 __M, __m128i __A)

VPBROADCASTW zmm {k}{z}, xmm EVEX.512 -mavx512bw

_mm512_maskz_set1_epi16 __m512i _mm512_maskz_set1_epi16(__mmask32 __M, short __A)

VPBROADCASTW zmm {k}{z}, r32 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.