Instruction
VPBROADCASTW
Copies one word from a register or memory to every word of a vector.
VPBROADCASTW copies one word to every word of a vector: 8, 16 or 32
copies of the low word of an XMM register or of a word in memory, or, in
the EVEX forms of AVX512BW, of the low 16 bits of a 32-bit
general-purpose register. VPBROADCASTD describes
the family and how the sources differ by encoding, and
VPBROADCASTB what the byte form is used for. On
Zen 5, vpbroadcastw ymm0{k4}{z}, ecx wrote 46C2h, the low word of ECX,
into the ten elements whose bits are set in the low 16 bits of K4
(6DE5h) and zeroed the other six, and every recorded XMM and YMM form
cleared the register above the vector it wrote.
In compiled code
In our builds at -O2, GCC 14 and Clang 23 compile _mm256_set1_epi16(x)
and a loop adding a run-time int16_t to every element of an array to
VMOVD and VPBROADCASTW with -march=x86-64-v3, and to
VPBROADCASTW straight from the register with -march=x86-64-v4. A word
already in memory, _mm256_set1_epi16(*p), is the memory form in both,
which reads just those two bytes at any alignment.
A constant is another matter. For _mm256_add_epi16(a, _mm256_set1_epi16(0x1234)), GCC builds 12341234h in a general-purpose
register and broadcasts it as a doubleword with VPBROADCASTD, since two
copies of the word make one doubleword; Clang adds a 32-byte constant
from memory with VPADDW, without any broadcast.
Before AVX2 there is no word broadcast. For the SSE2 baseline,
_mm_set1_epi16(x) is a MOVD and two shuffles: GCC interleaves the
register with itself by PUNPCKLWD and copies the
doubleword with PSHUFD, Clang fills the low four words
with PSHUFLW and copies them with PSHUFD. With SSSE3,
GCC uses one PSHUFB with a constant selector.
AMD’s latency spreadsheet for Zen 5 gives the 128-bit VEX form a latency of one cycle on all four vector pipes and the 256-bit VEX form one cycle on two of them, and lists the forms with a general-purpose source as two macro-ops. VPBROADCASTQ does the same for quadwords, and VPBROADCASTMW2D copies a mask register into every doubleword instead.
In the optimization guide
What the optimization guide says about VPBROADCASTW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.
Skylake to Cooper Lake
- AVX-512 and frequency on the servers: A broadcast of a 32-bit or 64-bit element from memory runs on the load ports, sparing port 5; a 16-bit one still goes through port 5, so it gains nothing from the memory form.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPBROADCASTW xmm, m16
VPBROADCASTW_XMMdq_MEMw | VEX.128.66.0F38.W0 79 /r | AVX2 |
VPBROADCASTW xmm, xmm
VPBROADCASTW_XMMdq_XMMw | VEX.128.66.0F38.W0 79 /r | AVX2 |
VPBROADCASTW ymm, m16
VPBROADCASTW_YMMqq_MEMw | VEX.256.66.0F38.W0 79 /r | AVX2 |
VPBROADCASTW ymm, xmm
VPBROADCASTW_YMMqq_XMMw | VEX.256.66.0F38.W0 79 /r | AVX2 |
VPBROADCASTW xmm {k}{z}, xmm
VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 | EVEX.128.66.0F38.W0 79 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTW xmm {k}{z}, m16
VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 | EVEX.128.66.0F38.W0 79 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTW xmm {k}{z}, r32
VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 | EVEX.128.66.0F38.W0 7B /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTW ymm {k}{z}, xmm
VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 | EVEX.256.66.0F38.W0 79 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTW ymm {k}{z}, m16
VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 | EVEX.256.66.0F38.W0 79 /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTW ymm {k}{z}, r32
VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 | EVEX.256.66.0F38.W0 7B /r | AVX10.1 or AVX512BW + AVX512VL |
VPBROADCASTW zmm {k}{z}, xmm
VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 | EVEX.512.66.0F38.W0 79 /r | AVX10.1 or AVX512BW |
VPBROADCASTW zmm {k}{z}, m16
VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 | EVEX.512.66.0F38.W0 79 /r | AVX10.1 or AVX512BW |
VPBROADCASTW zmm {k}{z}, r32
VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 | EVEX.512.66.0F38.W0 7B /r | AVX10.1 or AVX512BW |
Latency and throughput
| Model | xmm, m16xmm {k}{z}, m16no mask | xmm, xmm | ymm, m16 | ymm, xmmymm {k}{z}, xmmno maskzmm {k}{z}, xmmno mask | xmm {k}{z}, xmmno mask | xmm {k}{z}, xmmwith a mask, zeroing | xmm {k}{z}, m16with a mask, zeroing | xmm {k}{z}, r32 | ymm {k}{z}, xmmwith a mask, zeroingymm {k}{z}, r32zmm {k}{z}, xmmwith a mask, zeroingzmm {k}{z}, r32 | ymm {k}{z}, m16no maskzmm {k}{z}, m16no mask | ymm {k}{z}, m16with a mask, zeroingzmm {k}{z}, m16with a mask, zeroing |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Haswell, Broadwell | 9 / 1p015 | 3 / 1p5 | 9 / 1p015 | 3 / 1p5 | |||||||
| Skylake | 7 / 1p5 | 3 / 1p5 | 8 / 1p5 | 3 / 1p5 | |||||||
| Skylake-SP, Ice Lake | 7 / 1p5 | 3 / 1p5 | 8 / 1p5 | 3 / 1p5 | 1 / 1p5 | 1 / 1p5 | 7 / 1p5 | 1 / 1p5 | 3 / 1p5 | 8 / 1p5 | 8 / 1p5 |
| Alder Lake | 8 / 1p5 | 1 / 1p5 | 9 / 1p5 | 3 / 1p5 | |||||||
| Sapphire Rapids | 8 / 1p5 | 1 / 1p5 | 9 / 1p5 | 3 / 1p5 | 1 / 1p5 | 3 / 1p5 | 11 / 1p5 | 5 / 1p5 | 5 / 1p5 | 9 / 1p5 | 11 / 1p5 |
| Lunar Lake | 6 / 2p20 p21 p22 | 1 / 0.33p135 | 7 / 2.33p20 p21 p22 | 3 / 0.5V2 V3 | |||||||
| Zen | 8 / 1FPU1 FPU2 | 1 / 0.5FPU1 FPU2 | 8 / 2FPU1 | 2 / 1FPU1 FPU2 | |||||||
| Zen 2 | 8 / 1FPU1 FPU2 | 1 / 0.5FPU1 FPU2 | 8 / 2FPU1 | 2 / 0.5FPU1 FPU2 | |||||||
| Zen 3 | 8 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 2 / 1FP1 | |||||||
| Zen 4 | 8 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 1 / 11FP1 | 1 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 8 / 0.5FP1 FP2 | 1 / 0.5FP1 FP2 | 1 / 1FP1 | 8 / 1FP1 | 8 / 1FP1 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown for the ymm form; the xmm and zmm forms work the same on 8 and 32 words. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result words 15 to 0: a0, unchanged (bit 14 of k1 is 0), a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 16):
if k1[i]: # 1 without a write mask
zmm1.w[i] = src2.w[0]
elif zeroing:
zmm1.w[i] = 0
# else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 13 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPBROADCASTW xmm, xmm/m16 VPBROADCASTW ymm, xmm/m16 | ||
xmm, ymm | explicit | write |
xmm/m16 | explicit | read |
VPBROADCASTW xmm {k}{z}, xmm/m16 VPBROADCASTW ymm {k}{z}, xmm/m16 VPBROADCASTW zmm {k}{z}, xmm/m16 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m16 | explicit | read |
VPBROADCASTW xmm {k}{z}, r32 VPBROADCASTW ymm {k}{z}, r32 VPBROADCASTW zmm {k}{z}, r32 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
r32 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- VEX forms
avx-type-6VPBROADCASTW xmm {k}{z}, xmm/m16VPBROADCASTW ymm {k}{z}, xmm/m16VPBROADCASTW zmm {k}{z}, xmm/m16AVX512-E6VPBROADCASTW xmm {k}{z}, r32VPBROADCASTW ymm {k}{z}, r32VPBROADCASTW zmm {k}{z}, r32AVX512-E7NM
Attributes
What else XED records about the forms. How to read.
- EVEX forms
- write masking
- EVEX memory forms
- memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPBROADCASTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_broadcastw_epi16
__m128i _mm_broadcastw_epi16(__m128i __X) |
|
_mm_set1_pbh
__m128bh _mm_set1_pbh(__bf16 bf) |
|
_mm_set1_ph
__m128h _mm_set1_ph(_Float16 __h) |
|
_mm_mask_broadcastw_epi16
__m128i _mm_mask_broadcastw_epi16(__m128i __O, __mmask8 __M, __m128i __A) |
|
_mm_mask_set1_epi16
__m128i _mm_mask_set1_epi16(__m128i __O, __mmask8 __M, short __A) |
|
_mm_maskz_broadcastw_epi16
__m128i _mm_maskz_broadcastw_epi16(__mmask8 __M, __m128i __A) |
|
_mm_maskz_set1_epi16
__m128i _mm_maskz_set1_epi16(__mmask8 __M, short __A) |
|
_mm256_broadcastw_epi16
__m256i _mm256_broadcastw_epi16(__m128i __X) |
|
_mm256_set1_pbh
__m256bh _mm256_set1_pbh(__bf16 bf) |
|
_mm256_set1_ph
__m256h _mm256_set1_ph(_Float16 __h) |
|
_mm256_mask_broadcastw_epi16
__m256i _mm256_mask_broadcastw_epi16(__m256i __O, __mmask16 __M, __m128i __A) |
|
_mm256_mask_set1_epi16
__m256i _mm256_mask_set1_epi16(__m256i __O, __mmask16 __M, short __A) |
|
_mm256_maskz_broadcastw_epi16
__m256i _mm256_maskz_broadcastw_epi16(__mmask16 __M, __m128i __A) |
|
_mm256_maskz_set1_epi16
__m256i _mm256_maskz_set1_epi16(__mmask16 __M, short __A) |
|
_mm512_broadcastw_epi16
__m512i _mm512_broadcastw_epi16(__m128i __A) |
|
_mm512_set1_pbh
__m512bh _mm512_set1_pbh(__bf16 bf) |
|
_mm512_set1_ph
__m512h _mm512_set1_ph(_Float16 __h) |
|
_mm512_mask_broadcastw_epi16
__m512i _mm512_mask_broadcastw_epi16(__m512i __O, __mmask32 __M, __m128i __A) |
|
_mm512_mask_set1_epi16
__m512i _mm512_mask_set1_epi16(__m512i __O, __mmask32 __M, short __A) |
|
_mm512_maskz_broadcastw_epi16
__m512i _mm512_maskz_broadcastw_epi16(__mmask32 __M, __m128i __A) |
|
_mm512_maskz_set1_epi16
__m512i _mm512_maskz_set1_epi16(__mmask32 __M, short __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX2 | AVX2 | Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 |
AVX512BW_128 | AVX10.1 or AVX512BW + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6 |
AVX512BW_256 | Same as AVX512BW_128 | Same as AVX512BW_128 |
AVX512BW_512 | AVX10.1 or AVX512BW | Same as AVX512BW_128 |
More AVX2 instructions
- VPACKUSWB
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDD
- VPBLENDVB
- VPBLENDW
- VPBROADCASTB
- VPBROADCASTD
- VPBROADCASTQ
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPERM2I128
- VPERMD
- VPERMPD
- VPERMPS
- VPERMQ
- VPGATHERDD
- VPGATHERDQ
- VPGATHERQD
- VPGATHERQQ
- VPHADDD
- VPHADDSW
- VPHADDW
More AVX10.1 instructions
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPANDD
- VPANDND
- VPANDNQ
- VPANDQ
- VPAVGB
- VPAVGW
- VPBLENDMB
- VPBLENDMD
- VPBLENDMQ
- VPBLENDMW
- VPBROADCASTB
- VPBROADCASTD
- VPBROADCASTMB2Q
- VPBROADCASTMW2D
- VPBROADCASTQ
- VPCLMULQDQ
- VPCMPB
- VPCMPD
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPQ
- VPCMPUB
- VPCMPUD
- VPCMPUQ
- VPCMPUW
- VPCMPW
- VPCOMPRESSB
- VPCOMPRESSD
- VPCOMPRESSQ
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-442 (VPBROADCAST); Volume 2C, page 5-451 (VPBROADCASTB/
W/ D/ Q) - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.