x86-64.net

Instruction

VPCLMULQDQ

Carry-less multiplies one quadword of each source, chosen by an immediate, into a 128-bit product in each 128-bit lane.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPCLMULQDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPCLMULQDQ xmm, xmm, xmm, imm8 VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMbVEX.128.66.0F3A.WIG 44 /r ibAVX
VPCLMULQDQ xmm, xmm, m128, imm8 VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMbVEX.128.66.0F3A.WIG 44 /r ibAVX
VPCLMULQDQ ymm, ymm, ymm, imm8 VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8VEX.256.66.0F3A.WIG 44 /r ibVPCLMULQDQ
VPCLMULQDQ ymm, ymm, m256, imm8 VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8VEX.256.66.0F3A.WIG 44 /r ibVPCLMULQDQ
VPCLMULQDQ xmm, xmm, xmm, imm8 VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512EVEX.128.66.0F3A.WIG 44 /r ibAVX10.1 + VPCLMULQDQ or VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL
VPCLMULQDQ xmm, xmm, m128, imm8 VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512EVEX.128.66.0F3A.WIG 44 /r ibAVX10.1 + VPCLMULQDQ or VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL
VPCLMULQDQ ymm, ymm, ymm, imm8 VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512EVEX.256.66.0F3A.WIG 44 /r ibAVX10.1 + VPCLMULQDQ or VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL
VPCLMULQDQ ymm, ymm, m256, imm8 VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512EVEX.256.66.0F3A.WIG 44 /r ibAVX10.1 + VPCLMULQDQ or VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL
VPCLMULQDQ zmm, zmm, zmm, imm8 VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512EVEX.512.66.0F3A.WIG 44 /r ibAVX10.1 + VPCLMULQDQ or VPCLMULQDQ + PCLMULQDQ + AVX512F
VPCLMULQDQ zmm, zmm, m512, imm8 VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512EVEX.512.66.0F3A.WIG 44 /r ibAVX10.1 + VPCLMULQDQ or VPCLMULQDQ + PCLMULQDQ + AVX512F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCLMULQDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_clmulepi64_si128 __m128i _mm_clmulepi64_si128(__m128i X, __m128i Y, const char I)

VPCLMULQDQ xmm, xmm, xmm, imm8 VEX.128 -mavx -mpclmulwith AVX enabled

_mm256_clmulepi64_epi128 __m256i _mm256_clmulepi64_epi128(__m256i A, __m256i B, const char I)

VPCLMULQDQ ymm, ymm, ymm, imm8 VEX.256 -mvpclmulqdq

VPCLMULQDQ ymm, ymm, ymm, imm8 VEX.256 -mavx -mvpclmulqdqwith AVX enabled

_mm512_clmulepi64_epi128 __m512i _mm512_clmulepi64_epi128(__m512i A, __m512i B, const char I)

VPCLMULQDQ zmm, zmm, zmm, imm8 EVEX.512 -mavx512f -mvpclmulqdq

VPCLMULQDQ zmm, zmm, zmm, imm8 EVEX.512 -mavx -mavx512f -mvpclmulqdqwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
VPCLMULQDQ

VPCLMULQDQ
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ

Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest
AVX512_VPCLMULQDQ_128

AVX10.1 + VPCLMULQDQ
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ
CPUID.01H:ECX[1] PCLMULQDQ
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VPCLMULQDQ_256

AVX10.1 + VPCLMULQDQ
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

VPCLMULQDQ + PCLMULQDQ + AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ
CPUID.01H:ECX[1] PCLMULQDQ
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_VPCLMULQDQ_512

AVX10.1 + VPCLMULQDQ
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

VPCLMULQDQ + PCLMULQDQ + AVX512F
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ
CPUID.01H:ECX[1] PCLMULQDQ
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.