VPCLMULQDQ

VPCLMULQDQ is the VEX and EVEX form of PCLMULQDQ, the carry-less multiplication of two quadwords into a 128-bit product. That page explains the arithmetic, the immediate and the uses in GHASH and CRCs. The wider forms repeat the operation in every 128-bit lane: lane i multiplies a quadword of lane i of the first source by one of lane i of the second, chosen by bits 0 and 4 of the same immediate for all lanes, and writes its own 128-bit product. A 512-bit VPCLMULQDQ therefore computes four independent products, the “up to 4x” that Intel’s optimization manual expects for GHASH (Section 19.2).

One name, two feature bits#

The 128-bit VEX form predates the VPCLMULQDQ feature bit and is detected like the VEX-encoded AES instructions, from the PCLMULQDQ bit and the AVX checks (Intel’s optimization manual, Section 5.1.10). Checking only the VPCLMULQDQ bit for it would refuse processors that run it. The EVEX forms take no write mask and no broadcast.

The compilers follow the same split. At -O2, GCC 14 and Clang 23 emit the 128-bit form for _mm_clmulepi64_si128 with -mavx -mpclmul, but -march=x86-64-v3 and -march=x86-64-v4 include neither VPCLMULQDQ nor PCLMULQDQ: _mm256_clmulepi64_epi128 needs -mvpclmulqdq on top, and _mm512_clmulepi64_epi128 that and AVX-512F. -march=znver4 and later enable all of them.

Recorded on Zen 5#

The cases recorded on Zen 5 run every form. With immediate EEh, whose bits 0 and 4 are clear, the low quadwords were chosen and the other bits ignored; all ones squared gave 5555…5555h, the bits spread to the even positions, as squaring does without carries. A 512-bit case with immediate 13h multiplied the high quadwords of each lane separately: 1 times 1 in one lane gave 1, and 8 times 8 in the next gave 40h.

AMD’s Zen 5 guide lists VPCLMULQDQ as four macro-ops with a latency of four cycles and one instruction every two cycles at every width, the same as the legacy form, so the wider forms do more products in the same time.

In the optimization guide

What the optimization guide says about VPCLMULQDQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Ice Lake to Rocket Lake

• Vectors and AVX-512: VPCLMULQDQ does four carry-less multiplications at once in a 512-bit register, up to four times the rate of PCLMULQDQ, for the GHASH of AES-GCM.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 128):
    x = zmm2.q[2 * i + (imm8 & 1)]
    y = src3.q[2 * i + (imm8 >> 4 & 1)]
    zmm1.dq[i] = clmul(x, y)
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCLMULQDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD

All 253 AVX instructions

More AVX10.1 instructions

• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW

All 686 AVX10.1 instructions