VPCMOV instruction (XOP)

In the optimization guide

What the optimization guide says about VPCMOV, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

Vectors and floating point: XOP adds integer instructions of three and four operands: VPPERM, which selects bytes from two registers, VPCMOV, a bitwise select, rotates, shifts by a count per element, compares into masks and multiply-accumulates.

Forms

Every encoding of VPCMOV that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPCMOV xmm, xmm, m128, xmm` VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq	`XOP.128.NP.08.W0 A2 /r /is4`	XOP
`VPCMOV xmm, xmm, xmm, xmm` VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq	`XOP.128.NP.08.W0 A2 /r /is4` `XOP.128.NP.08.W1 A2 /r /is4`	XOP
`VPCMOV xmm, xmm, xmm, m128` VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq	`XOP.128.NP.08.W1 A2 /r /is4`	XOP
`VPCMOV ymm, ymm, m256, ymm` VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq	`XOP.256.NP.08.W0 A2 /r /is4`	XOP
`VPCMOV ymm, ymm, ymm, ymm` VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq	`XOP.256.NP.08.W0 A2 /r /is4` `XOP.256.NP.08.W1 A2 /r /is4`	XOP
`VPCMOV ymm, ymm, ymm, m256` VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq	`XOP.256.NP.08.W1 A2 /r /is4`	XOP

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 2 and 4 quadwords in the xmm and ymm forms. The sources are drawn above the result, each element in its own column.

Result quadword i comes from quadword i of xmm2, xmm3 and xmm4. Result quadwords 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 11 & 1:
    fault(UD)  # CPUID: no XOP
for i in range(VL // 64):
    a = ymm2.q[i]
    b = src3.q[i]
    c = src4.q[i]
    ymm1.q[i] = a & c | b & ~c
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 6 cases. Its cases ran where CPUID reported no XOP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPCMOV xmm, xmm, xmm/m128, xmm` `VPCMOV ymm, ymm, ymm/m256, ymm`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`xmm, ymm`	explicit	read
`VPCMOV xmm, xmm, xmm, m128` `VPCMOV ymm, ymm, ymm, m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm, ymm`	explicit	read
`m128/256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMOV, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmov_si128` `__m128i _mm_cmov_si128(__m128i __A, __m128i __B, __m128i __C)`	`VPCMOV xmm, xmm, xmm, xmm` XOP.128 -mxop
`_mm256_cmov_si256` `__m256i _mm256_cmov_si256(__m256i __A, __m256i __B, __m256i __C)`	`VPCMOV ymm, ymm, ymm, ymm` XOP.256 -mxop

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`XOP` XOP	XOP `CPUID.80000001H:ECX[11]` XOP	Bulldozer, Piledriver

More XOP instructions

All 55 XOP instructions