Instruction
VPCMPB
Compares packed signed bytes with a predicate chosen by an immediate and writes the results to a mask register.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VPCMPB compares 16, 32 or 64 pairs of signed bytes and writes one bit per pair to a mask register. The immediate picks the test, of which only bits 2:0 count, as on VPCMPD’s page: 0 equal, 1 less, 2 less or equal, 4 not equal, 5 greater or equal, 6 greater, 3 false and 7 true. VPCMPUB is the unsigned twin. Both need AVX512BW (or AVX10.1) and take no broadcast operand. SSE and AVX compare bytes only with PCMPEQB and PCMPGTB, which write a vector of all-ones and zero bytes.
Recorded on Zen 5
- Signed order. In
vpcmpb k6{k1}, zmm17, zmm30, 0x1, less than, the pair 80h and 01h set its bit, -128 being below 1, and 7Fh against FFh left it clear, 127 not being below -1; an unsigned compare would answer both the other way. - The write mask clears. Only the 32 elements that K1 selected could be set, and every bit outside K1 came out 0, whatever K6 held.
- Predicate 7 copies the mask.
vpcmpb k1{k5}, xmm24, xmm3, 0x7gave D5E1h, the low 16 bits of K5, and cleared bits 63:16. - Bits 7:3 are ignored.
vpcmpb k3, ymm9, ymm9, 0xatested less or equal, as 2 does, and gave FFFFFFFFh for 32 equal pairs.
In compiled code
With -march=x86-64-v4, GCC 14 at -O2 compiles every byte compare
intrinsic on registers to VPCMPB with its predicate,
_mm512_cmpeq_epi8_mask and _mm512_cmpgt_epi8_mask included, while
Clang 23 keeps VPCMPEQB and
VPCMPGTB for those and uses VPCMPB, printed
vpcmpneqb or vpcmpnltb, for not equal and greater or equal. Less
than swaps the operands into VPCMPGTB, unless the second source is in
memory: for o[i] = a[i] < b[i] ? a[i] : 0 over int8_t arrays, Clang
emits vpcmpltb with b[i] as the memory operand on YMM registers, and
GCC VPCMPB with predicate 1 on ZMM, each followed by a zero-masked
VMOVDQU8.
AMD’s Zen 5 latency spreadsheet lists VPCMPB as one macro-op on pipes FP1 or FP2, two for a memory source, with 3, 4 and 6 cycles of latency for XMM, YMM and ZMM, as VPCMPUB.
In the optimization guide
What the optimization guide says about VPCMPB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.
Zen 4
- Vectors and floating point: An AVX-512 compare that writes a mask register, such as VPCMPD, takes 3, 4 or 5 cycles for 128, 256 or 512 bits, where the older compares into a vector register take one cycle for integers and two for floats. sources differ
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPCMPB k {k}, xmm, xmm, imm8
VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 | EVEX.128.66.0F3A.W0 3F /r ib | AVX10.1 or AVX512BW + AVX512VL |
VPCMPB k {k}, xmm, m128, imm8
VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 | EVEX.128.66.0F3A.W0 3F /r ib | AVX10.1 or AVX512BW + AVX512VL |
VPCMPB k {k}, ymm, ymm, imm8
VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 | EVEX.256.66.0F3A.W0 3F /r ib | AVX10.1 or AVX512BW + AVX512VL |
VPCMPB k {k}, ymm, m256, imm8
VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 | EVEX.256.66.0F3A.W0 3F /r ib | AVX10.1 or AVX512BW + AVX512VL |
VPCMPB k {k}, zmm, zmm, imm8
VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 | EVEX.512.66.0F3A.W0 3F /r ib | AVX10.1 or AVX512BW |
VPCMPB k {k}, zmm, m512, imm8
VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 | EVEX.512.66.0F3A.W0 3F /r ib | AVX10.1 or AVX512BW |
Latency and throughput
| Model | k {k}, xmm, xmm, imm8k {k}, ymm, ymm, imm8 | k {k}, xmm, m128, imm8 | k {k}, ymm, m256, imm8k {k}, zmm, m512, imm8 | k {k}, zmm, zmm, imm8 |
|---|---|---|---|---|
| Skylake-SP, Ice Lake | 4 / 1p5 | 10 / 1p5 | 11 / 1p5 | 4 / 1p5 |
| Sapphire Rapids | 3 / 1p5 | 3 / 1p5 | 3 / 1p5 | 3 / 1p5 |
| Zen 4 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 FP2 FP3 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Where a bit of the write mask k2 is 0, the result bit is 0. Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms.
Bit i of k1 comes from byte i of xmm2 and xmm3. Result bits 7 to 0: r7, 0 (bit 6 of k2 is 0), r5, r4, r3, r2, r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 8):
sa = zmm2.sb[i]
sb = src3.sb[i]
k1[i] = k2[i] and compare(imm8, sa, sb)
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 false, 4 !=, 5 >=, 6 >, 7 true
# the other bits of k1 are clearedRun on AMD Zen 5 (EPYC 9645): 6 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPCMPB k {k}, xmm, xmm/m128, imm8 VPCMPB k {k}, ymm, ymm/m256, imm8 VPCMPB k {k}, zmm, zmm/m512, imm8 | ||
k | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm, ymm, zmm | explicit | read |
xmm/m128, ymm/m256, zmm/m512 | explicit | read |
imm8 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking
- Memory forms
- memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPCMPB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cmp_epi8_mask
__mmask16 _mm_cmp_epi8_mask(__m128i a, __m128i b, const int p) |
|
_mm_mask_cmp_epi8_mask
__mmask16 _mm_mask_cmp_epi8_mask(__mmask16 m, __m128i a, __m128i b, const int p) |
|
_mm_cmpge_epi8_mask
__mmask16 _mm_cmpge_epi8_mask(__m128i A, __m128i B) |
|
_mm_mask_cmpge_epi8_mask
__mmask16 _mm_mask_cmpge_epi8_mask(__mmask16 k, __m128i A, __m128i B) |
|
_mm_cmple_epi8_mask
__mmask16 _mm_cmple_epi8_mask(__m128i A, __m128i B) |
|
_mm_mask_cmple_epi8_mask
__mmask16 _mm_mask_cmple_epi8_mask(__mmask16 k, __m128i A, __m128i B) |
|
_mm_cmpneq_epi8_mask
__mmask16 _mm_cmpneq_epi8_mask(__m128i A, __m128i B) |
|
_mm_mask_cmpneq_epi8_mask
__mmask16 _mm_mask_cmpneq_epi8_mask(__mmask16 k, __m128i A, __m128i B) |
|
_mm_cmpneq_epu8_mask
__mmask16 _mm_cmpneq_epu8_mask(__m128i A, __m128i B) |
|
_mm_mask_cmpneq_epu8_mask
__mmask16 _mm_mask_cmpneq_epu8_mask(__mmask16 k, __m128i A, __m128i B) |
|
_mm256_cmp_epi8_mask
__mmask32 _mm256_cmp_epi8_mask(__m256i a, __m256i b, const int p) |
|
_mm256_mask_cmp_epi8_mask
__mmask32 _mm256_mask_cmp_epi8_mask(__mmask32 m, __m256i a, __m256i b, const int p) |
|
_mm256_cmpge_epi8_mask
__mmask32 _mm256_cmpge_epi8_mask(__m256i A, __m256i B) |
|
_mm256_mask_cmpge_epi8_mask
__mmask32 _mm256_mask_cmpge_epi8_mask(__mmask32 k, __m256i A, __m256i B) |
|
_mm256_cmple_epi8_mask
__mmask32 _mm256_cmple_epi8_mask(__m256i A, __m256i B) |
|
_mm256_mask_cmple_epi8_mask
__mmask32 _mm256_mask_cmple_epi8_mask(__mmask32 k, __m256i A, __m256i B) |
|
_mm256_cmpneq_epi8_mask
__mmask32 _mm256_cmpneq_epi8_mask(__m256i A, __m256i B) |
|
_mm256_mask_cmpneq_epi8_mask
__mmask32 _mm256_mask_cmpneq_epi8_mask(__mmask32 k, __m256i A, __m256i B) |
|
_mm256_cmpneq_epu8_mask
__mmask32 _mm256_cmpneq_epu8_mask(__m256i A, __m256i B) |
|
_mm256_mask_cmpneq_epu8_mask
__mmask32 _mm256_mask_cmpneq_epu8_mask(__mmask32 k, __m256i A, __m256i B) |
|
_mm512_cmp_epi8_mask
__mmask64 _mm512_cmp_epi8_mask(__m512i a, __m512i b, const int p) |
|
_mm512_mask_cmp_epi8_mask
__mmask64 _mm512_mask_cmp_epi8_mask(__mmask64 m, __m512i a, __m512i b, const int p) |
|
_mm512_cmpge_epi8_mask
__mmask64 _mm512_cmpge_epi8_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmpge_epi8_mask
__mmask64 _mm512_mask_cmpge_epi8_mask(__mmask64 k, __m512i A, __m512i B) |
|
_mm512_cmple_epi8_mask
__mmask64 _mm512_cmple_epi8_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmple_epi8_mask
__mmask64 _mm512_mask_cmple_epi8_mask(__mmask64 k, __m512i A, __m512i B) |
|
_mm512_cmpneq_epi8_mask
__mmask64 _mm512_cmpneq_epi8_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmpneq_epi8_mask
__mmask64 _mm512_mask_cmpneq_epi8_mask(__mmask64 k, __m512i A, __m512i B) |
|
_mm512_cmpneq_epu8_mask
__mmask64 _mm512_cmpneq_epu8_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmpneq_epu8_mask
__mmask64 _mm512_mask_cmpneq_epu8_mask(__mmask64 k, __m512i A, __m512i B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX512BW_128 | AVX10.1 or AVX512BW + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6 |
AVX512BW_256 | Same as AVX512BW_128 | Same as AVX512BW_128 |
AVX512BW_512 | AVX10.1 or AVX512BW | Same as AVX512BW_128 |
More AVX10.1 instructions
- VPADDUSW
- VPADDW
- VPALIGNR
- VPANDD
- VPANDND
- VPANDNQ
- VPANDQ
- VPAVGB
- VPAVGW
- VPBLENDMB
- VPBLENDMD
- VPBLENDMQ
- VPBLENDMW
- VPBROADCASTB
- VPBROADCASTD
- VPBROADCASTMB2Q
- VPBROADCASTMW2D
- VPBROADCASTQ
- VPBROADCASTW
- VPCLMULQDQ
- VPCMPD
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPQ
- VPCMPUB
- VPCMPUD
- VPCMPUQ
- VPCMPUW
- VPCMPW
- VPCOMPRESSB
- VPCOMPRESSD
- VPCOMPRESSQ
- VPCOMPRESSW
- VPCONFLICTD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-456 (VPCMPB/
VPCMPUB) - Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.