VPCMPD

VPCMPD compares 4, 8 or 16 pairs of signed doublewords and writes one bit per pair to a mask register, where PCMPEQD and PCMPGTD write a vector of all-ones and zero elements. Bits 2:0 of the immediate choose the test, so every ordering is one instruction, where SSE needed swapped operands or a NOT. In vpcmpd k1{k2}, a, b, imm8, a is the first source, a register, and b the second, a register, memory or a broadcast element:

VPCMPUD is the unsigned twin; for 0 and 4 the two agree.

The mask it writes#

A write mask does not merge here: an element it leaves out gets a 0, so vpcmpd k1{k2}, ... gives the AND of k2 and the compare, which chains conditions without KANDW. The mask bits above the element count are cleared. Intel’s optimization manual builds the mask for a loop’s last iterations this way (Section 17.2.6, Example 17-9): a register of element indices, compared less-than with the broadcast count of elements left, selects the elements below that count for the masked loads and stores.

In compiled code#

GCC 14 and Clang 23 at -O2 with -mavx512f compile _mm512_cmplt_epi32_mask and its kin differently. GCC emits VPCMPD with the immediate for every test. Clang takes the shorter opcodes without an immediate where they fit: equality becomes the EVEX form of VPCMPEQD, greater-than VPCMPGTD, and less-than VPCMPGTD with the operands swapped; it prints the other VPCMPDs with the aliases above, folds a broadcast into the {1to16} operand, and turns tests 3 and 7 into constants. A disassembler such as objdump prints vpcmpeqd for both encodings of equality, VPCMPD with 0 and the older opcode.

AMD’s Zen 5 guide lists VPCMPD with a latency of 3, 4 and 6 cycles for XMM, YMM and ZMM registers, against 1 for the VEX compares that write a vector.

In the optimization guide

What the optimization guide says about VPCMPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: An AVX-512 compare that writes a mask register, such as VPCMPD, takes 3, 4 or 5 cycles for 128, 256 or 512 bits, where the older compares into a vector register take one cycle for integers and two for floats. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    sa = zmm2.sd[i]
    sb = src3.sd[i]
    k1[i] = k2[i] and compare(imm8, sa, sb)
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 false, 4 !=, 5 >=, 6 >, 7 true
# m32bcst: src3.d[i] is the m32 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPADDW
• VPALIGNR
• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ

All 686 AVX10.1 instructions