Instruction
VPCMPEQB
Compares packed bytes for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.
VPCMPEQB compares bytes for equality: the VEX form writes FFh or 00h per byte into a vector, as SSE2’s PCMPEQB does, and the EVEX form a bit per byte into a mask register. VPCMPEQD describes the two encodings, and the PCMPEQB page the byte search with VPMOVMSKB and the all-ones idiom. The byte width adds:
- AVX512BW and 64 bits. The EVEX form needs AVX512BW (or AVX10.1)
and fills up to 64 mask bits, clearing the rest: on Zen 5,
{evex} vpcmpeqb k1, ymm5, ymm5set K1 to FFFFFFFFh, 32 ones, whatever it held before. A write mask clears the bits it leaves out:vpcmpeqb k4{k1}, xmm0, xmm31found bytes 2, 5, 10, 11 and 15 equal, but of these K1 selected only bit 5, so K4 became 20h. - No broadcast. Like the other byte forms, the compare cannot repeat a byte from memory, so the wanted byte is spread first with VPBROADCASTB.
Counting bytes
A byte counter would overflow after 255 matches, so the subtraction of
-1 that counts doublewords does not carry over. For n += a[i] == k
over 1,024 bytes, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3
compare with VPCMPEQB, keep 1 per match with VPAND,
before or after widening into doubleword sums: GCC with VPMOVZXBW and
VPMOVZXWD from 32 compared bytes, Clang with
VPMOVZXBD from eight. With -march=x86-64-v4, GCC
compares into K1 with VPCMPB, predicate 0, and turns
the mask into bytes of 1 with a zero-masked VMOVDQU8.
Neither compiler vectorizes a search loop that returns at the first
match, if (a[i] == k) return i;: both keep it scalar, Clang unrolled
eight times. The vector search comes from intrinsics or a C library.
With a write mask, _mm512_mask_cmpeq_epi8_mask(m, a, b) becomes a
masked VPCMPB in GCC; Clang compares without the mask and ANDs the
result in a general-purpose register.
AMD’s latency spreadsheet for Zen 5 gives the vector form one cycle, four per cycle, and the mask form 3, 4 and 6 cycles for xmm, ymm and zmm sources, two per cycle. Zen 5’s 10 recorded cases cover every form, the EVEX ones masked and unmasked.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPCMPEQB xmm, xmm, m128
VPCMPEQB_XMMdq_XMMdq_MEMdq | VEX.128.66.0F.WIG 74 /r | AVX |
VPCMPEQB xmm, xmm, xmm
VPCMPEQB_XMMdq_XMMdq_XMMdq | VEX.128.66.0F.WIG 74 /r | AVX |
VPCMPEQB ymm, ymm, m256
VPCMPEQB_YMMqq_YMMqq_MEMqq | VEX.256.66.0F.WIG 74 /r | AVX2 |
VPCMPEQB ymm, ymm, ymm
VPCMPEQB_YMMqq_YMMqq_YMMqq | VEX.256.66.0F.WIG 74 /r | AVX2 |
VPCMPEQB k {k}, xmm, xmm
VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 | EVEX.128.66.0F.WIG 74 /r | AVX10.1 or AVX512BW + AVX512VL |
VPCMPEQB k {k}, xmm, m128
VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 | EVEX.128.66.0F.WIG 74 /r | AVX10.1 or AVX512BW + AVX512VL |
VPCMPEQB k {k}, ymm, ymm
VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 | EVEX.256.66.0F.WIG 74 /r | AVX10.1 or AVX512BW + AVX512VL |
VPCMPEQB k {k}, ymm, m256
VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 | EVEX.256.66.0F.WIG 74 /r | AVX10.1 or AVX512BW + AVX512VL |
VPCMPEQB k {k}, zmm, zmm
VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 | EVEX.512.66.0F.WIG 74 /r | AVX10.1 or AVX512BW |
VPCMPEQB k {k}, zmm, m512
VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 | EVEX.512.66.0F.WIG 74 /r | AVX10.1 or AVX512BW |
Latency and throughput
| Model | xmm, xmm, m128 | xmm, xmm, xmm | ymm, ymm, m256 | ymm, ymm, ymm | k {k}, xmm, xmmk {k}, ymm, ymm | k {k}, xmm, m128 | k {k}, ymm, m256k {k}, zmm, m512 | k {k}, zmm, zmm |
|---|---|---|---|---|---|---|---|---|
| Sandy Bridge | 7 / 0.5p15 | 1 / 0.5p15 | ||||||
| Haswell | 7 / 0.5p15 | 1 / 0.5p15 | 8 / 0.5p15 | 1 / 0.5p15 | ||||
| Broadwell | 6 / 0.5p15 | 1 / 0.5p15 | 7 / 0.5p15 | 1 / 0.5p15 | ||||
| Skylake | 7 / 0.5p01 | 1 / 0.5p01 | 8 / 0.5p01 | 1 / 0.5p01 | ||||
| Skylake-SP, Ice Lake | 7 / 0.5p01 | 1 / 0.5p01 | 8 / 0.5p01 | 1 / 0.5p01 | 4 / 1p5 | 10 / 1p5 | 11 / 1p5 | 4 / 1p5 |
| Alder Lake | 8 / 0.5p01 | 1 / 0.5p01 | 9 / 0.5p01 | 1 / 0.5p01 | ||||
| Sapphire Rapids | 8 / 0.5p01 | 1 / 0.5p01 | 9 / 0.5p01 | 1 / 0.5p01 | 3 / 1p5 | 3 / 1p5 | 3 / 1p5 | 3 / 1p5 |
| Lunar Lake | 7 / 2V0 V1 | 1 / 0.5V0 V1 | 8 / 2.33V0 V1 | 1 / 0.5V0 V1 | ||||
| Piledriver | 7 / 1.5FPMAL | 2 / 0.5FPMAL FPU2 FPU3 | ||||||
| Zen | 8 / 0.5FPU0 FPU1 FPU3 | 1 / 0.33FPU0 FPU1 FPU3 | 8 / 0.67FPU0 FPU1 FPU3 | 1 / 0.67FPU0 FPU1 FPU3 | ||||
| Zen 2 | 8 / 0.33FPU0 FPU1 FPU3 | 1 / 0.33FPU0 FPU1 FPU3 | 8 / 0.33FPU0 FPU1 FPU3 | 1 / 0.33FPU0 FPU1 FPU3 | ||||
| Zen 3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | ||||
| Zen 4 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.25FP0 FP1 FP2 FP3 | 1 / 0.251FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 FP2 FP3 |
| Jaguar | 6 / 1FPU0 FPU1 VALU0 VALU1 | 1 / 0.5FPU0 FPU1 VALU0 VALU1 | ||||||
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown: bytes 7 to 0. Every byte works alike: 16 and 32 bytes in the xmm and ymm forms.
Result byte i comes from byte i of xmm2 and xmm3. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.
Where a bit of the write mask k2 is 0, the result bit is 0. Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms.
Bit i of k1 comes from byte i of xmm2 and xmm3. Result bits 7 to 0: r7, 0 (bit 6 of k2 is 0), r5, r4, r3, r2, r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 8):
a = ymm2.b[i]
b = src3.b[i]
ymm1.b[i] = -1 if a == b else 0
# ymm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 4 cases.
for i in range(VL // 8):
k1[i] = k2[i] and zmm2.b[i] == src3.b[i]
# the other bits of k1 are clearedRun on AMD Zen 5 (EPYC 9645): 6 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPCMPEQB xmm, xmm, xmm/m128 VPCMPEQB ymm, ymm, ymm/m256 | ||
xmm, ymm | explicit | write |
xmm, ymm | explicit | read |
xmm/m128, ymm/m256 | explicit | read |
VPCMPEQB k {k}, xmm, xmm/m128 VPCMPEQB k {k}, ymm, ymm/m256 VPCMPEQB k {k}, zmm, zmm/m512 | ||
k | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm, ymm, zmm | explicit | read |
xmm/m128, ymm/m256, zmm/m512 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- VEX forms
avx-type-4- EVEX forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- EVEX forms
- write masking
- EVEX memory forms
- memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPCMPEQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cmpeq_epi8
__m128i _mm_cmpeq_epi8(__m128i __a, __m128i __b) |
|
_mm_cmpeq_epi8_mask
__mmask16 _mm_cmpeq_epi8_mask(__m128i A, __m128i B) |
|
_mm_mask_cmpeq_epi8_mask
__mmask16 _mm_mask_cmpeq_epi8_mask(__mmask16 k, __m128i A, __m128i B) |
|
_mm_cmpeq_epu8_mask
__mmask16 _mm_cmpeq_epu8_mask(__m128i A, __m128i B) |
|
_mm_mask_cmpeq_epu8_mask
__mmask16 _mm_mask_cmpeq_epu8_mask(__mmask16 k, __m128i A, __m128i B) |
|
_mm256_cmpeq_epi8
__m256i _mm256_cmpeq_epi8(__m256i __a, __m256i __b) |
|
_mm256_cmpeq_epi8_mask
__mmask32 _mm256_cmpeq_epi8_mask(__m256i A, __m256i B) |
|
_mm256_mask_cmpeq_epi8_mask
__mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i A, __m256i B) |
|
_mm256_cmpeq_epu8_mask
__mmask32 _mm256_cmpeq_epu8_mask(__m256i A, __m256i B) |
|
_mm256_mask_cmpeq_epu8_mask
__mmask32 _mm256_mask_cmpeq_epu8_mask(__mmask32 k, __m256i A, __m256i B) |
|
_mm512_cmpeq_epi8_mask
__mmask64 _mm512_cmpeq_epi8_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmpeq_epi8_mask
__mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i A, __m512i B) |
|
_mm512_cmpeq_epu8_mask
__mmask64 _mm512_cmpeq_epu8_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmpeq_epu8_mask
__mmask64 _mm512_mask_cmpeq_epu8_mask(__mmask64 k, __m512i A, __m512i B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More AVX instructions
- VPACKSSDW
- VPACKSSWB
- VPACKUSDW
- VPACKUSWB
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDVB
- VPBLENDW
- VPCLMULQDQ
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPESTRI
- VPCMPESTRM
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPISTRI
- VPCMPISTRM
- VPERM2F128
- VPERMILPD
- VPERMILPS
- VPEXTRB
- VPEXTRD
- VPEXTRQ
- VPEXTRW
- VPHADDD
- VPHADDSW
More AVX2 instructions
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDD
- VPBLENDVB
- VPBLENDW
- VPBROADCASTB
- VPBROADCASTD
- VPBROADCASTQ
- VPBROADCASTW
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPERM2I128
- VPERMD
- VPERMPD
- VPERMPS
- VPERMQ
- VPGATHERDD
- VPGATHERDQ
- VPGATHERQD
- VPGATHERQQ
- VPHADDD
- VPHADDSW
- VPHADDW
- VPHSUBD
More AVX10.1 instructions
- VPALIGNR
- VPANDD
- VPANDND
- VPANDNQ
- VPANDQ
- VPAVGB
- VPAVGW
- VPBLENDMB
- VPBLENDMD
- VPBLENDMQ
- VPBLENDMW
- VPBROADCASTB
- VPBROADCASTD
- VPBROADCASTMB2Q
- VPBROADCASTMW2D
- VPBROADCASTQ
- VPBROADCASTW
- VPCLMULQDQ
- VPCMPB
- VPCMPD
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPQ
- VPCMPUB
- VPCMPUD
- VPCMPUQ
- VPCMPUW
- VPCMPW
- VPCOMPRESSB
- VPCOMPRESSD
- VPCOMPRESSQ
- VPCOMPRESSW
- VPCONFLICTD
- VPCONFLICTQ
- VPDPBUSD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-245 (PCMPEQB/
PCMPEQW/ PCMPEQD) - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
- Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.