Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPCMPEQB compares bytes for equality: the VEX form writes FFh or 00h per byte into a vector, as SSE2’s PCMPEQB does, and the EVEX form a bit per byte into a mask register. VPCMPEQD describes the two encodings, and the PCMPEQB page the byte search with VPMOVMSKB and the all-ones idiom. The byte width adds:

  • AVX512BW and 64 bits. The EVEX form needs AVX512BW (or AVX10.1) and fills up to 64 mask bits, clearing the rest: on Zen 5, {evex} vpcmpeqb k1, ymm5, ymm5 set K1 to FFFFFFFFh, 32 ones, whatever it held before. A write mask clears the bits it leaves out: vpcmpeqb k4{k1}, xmm0, xmm31 found bytes 2, 5, 10, 11 and 15 equal, but of these K1 selected only bit 5, so K4 became 20h.
  • No broadcast. Like the other byte forms, the compare cannot repeat a byte from memory, so the wanted byte is spread first with VPBROADCASTB.

Counting bytes

A byte counter would overflow after 255 matches, so the subtraction of -1 that counts doublewords does not carry over. For n += a[i] == k over 1,024 bytes, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 compare with VPCMPEQB, keep 1 per match with VPAND, before or after widening into doubleword sums: GCC with VPMOVZXBW and VPMOVZXWD from 32 compared bytes, Clang with VPMOVZXBD from eight. With -march=x86-64-v4, GCC compares into K1 with VPCMPB, predicate 0, and turns the mask into bytes of 1 with a zero-masked VMOVDQU8.

Neither compiler vectorizes a search loop that returns at the first match, if (a[i] == k) return i;: both keep it scalar, Clang unrolled eight times. The vector search comes from intrinsics or a C library.

With a write mask, _mm512_mask_cmpeq_epi8_mask(m, a, b) becomes a masked VPCMPB in GCC; Clang compares without the mask and ANDs the result in a general-purpose register.

AMD’s latency spreadsheet for Zen 5 gives the vector form one cycle, four per cycle, and the mask form 3, 4 and 6 cycles for xmm, ymm and zmm sources, two per cycle. Zen 5’s 10 recorded cases cover every form, the EVEX ones masked and unmasked.

Forms

Every encoding of VPCMPEQB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPCMPEQB xmm, xmm, m128 VPCMPEQB_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 74 /rAVX
VPCMPEQB xmm, xmm, xmm VPCMPEQB_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 74 /rAVX
VPCMPEQB ymm, ymm, m256 VPCMPEQB_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 74 /rAVX2
VPCMPEQB ymm, ymm, ymm VPCMPEQB_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 74 /rAVX2
VPCMPEQB k {k}, xmm, xmm VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512EVEX.128.66.0F.WIG 74 /rAVX10.1 or AVX512BW + AVX512VL
VPCMPEQB k {k}, xmm, m128 VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512EVEX.128.66.0F.WIG 74 /rAVX10.1 or AVX512BW + AVX512VL
VPCMPEQB k {k}, ymm, ymm VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512EVEX.256.66.0F.WIG 74 /rAVX10.1 or AVX512BW + AVX512VL
VPCMPEQB k {k}, ymm, m256 VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512EVEX.256.66.0F.WIG 74 /rAVX10.1 or AVX512BW + AVX512VL
VPCMPEQB k {k}, zmm, zmm VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512EVEX.512.66.0F.WIG 74 /rAVX10.1 or AVX512BW
VPCMPEQB k {k}, zmm, m512 VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512EVEX.512.66.0F.WIG 74 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128xmm, xmm, xmmymm, ymm, m256ymm, ymm, ymmk {k}, xmm, xmm
k {k}, ymm, ymm
k {k}, xmm, m128k {k}, ymm, m256
k {k}, zmm, m512
k {k}, zmm, zmm
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p014 / 1p510 / 1p511 / 1p54 / 1p5
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p013 / 1p53 / 1p53 / 1p53 / 1p5
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP3
Zen 48 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.251FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model, xmm form: AMD's spreadsheets give latency 3 for Zen 4 and Zen 5 (AMD 57647, row 2070; AMD 58455, row 192).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.VEX forms
VPCMPEQB: element by elementResult byte i comes from byte i of xmm2 and xmm3. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.…01234567xmm2a…r0r1r2r3r4r5r6r7xmm1…01234567xmm3or m128b

Shown: bytes 7 to 0. Every byte works alike: 16 and 32 bytes in the xmm and ymm forms.

Result byte i comes from byte i of xmm2 and xmm3. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

To a mask: each byte of the sources sets one bit of k1, bit i for byte i.EVEX forms
VPCMPEQB: a bit of k1 per elementBit i of k1 comes from byte i of xmm2 and xmm3. Result bits 7 to 0: r7, 0 (bit 6 of k2 is 0), r5, r4, r3, r2, r1, r0.11111110k2…r0r1r2r3r4r5r70k1…01234567xmm3or m128b

Where a bit of the write mask k2 is 0, the result bit is 0. Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms.

Bit i of k1 comes from byte i of xmm2 and xmm3. Result bits 7 to 0: r7, 0 (bit 6 of k2 is 0), r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VEX forms
for i in range(VL // 8):
    a = ymm2.b[i]
    b = src3.b[i]
    ymm1.b[i] = -1 if a == b else 0
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

EVEX forms
for i in range(VL // 8):
    k1[i] = k2[i] and zmm2.b[i] == src3.b[i]
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPCMPEQB xmm, xmm, xmm/m128 VPCMPEQB ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPCMPEQB k {k}, xmm, xmm/m128 VPCMPEQB k {k}, ymm, ymm/m256 VPCMPEQB k {k}, zmm, zmm/m512
kexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPEQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmpeq_epi8 __m128i _mm_cmpeq_epi8(__m128i __a, __m128i __b)

VPCMPEQB xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_cmpeq_epi8_mask __mmask16 _mm_cmpeq_epi8_mask(__m128i A, __m128i B)

VPCMPEQB k, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_mask_cmpeq_epi8_mask __mmask16 _mm_mask_cmpeq_epi8_mask(__mmask16 k, __m128i A, __m128i B)

VPCMPEQB k, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_cmpeq_epu8_mask __mmask16 _mm_cmpeq_epu8_mask(__m128i A, __m128i B)

VPCMPEQB k, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_mask_cmpeq_epu8_mask __mmask16 _mm_mask_cmpeq_epu8_mask(__mmask16 k, __m128i A, __m128i B)

VPCMPEQB k, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_cmpeq_epi8 __m256i _mm256_cmpeq_epi8(__m256i __a, __m256i __b)

VPCMPEQB ymm, ymm, ymm VEX.256 -mavx2

_mm256_cmpeq_epi8_mask __mmask32 _mm256_cmpeq_epi8_mask(__m256i A, __m256i B)

VPCMPEQB k, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_cmpeq_epi8_mask __mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i A, __m256i B)

VPCMPEQB k, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_cmpeq_epu8_mask __mmask32 _mm256_cmpeq_epu8_mask(__m256i A, __m256i B)

VPCMPEQB k, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_cmpeq_epu8_mask __mmask32 _mm256_mask_cmpeq_epu8_mask(__mmask32 k, __m256i A, __m256i B)

VPCMPEQB k, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_cmpeq_epi8_mask __mmask64 _mm512_cmpeq_epi8_mask(__m512i A, __m512i B)

VPCMPEQB k, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_cmpeq_epi8_mask __mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i A, __m512i B)

VPCMPEQB k, zmm, zmm EVEX.512 -mavx512bw

_mm512_cmpeq_epu8_mask __mmask64 _mm512_cmpeq_epu8_mask(__m512i A, __m512i B)

VPCMPEQB k, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_cmpeq_epu8_mask __mmask64 _mm512_mask_cmpeq_epu8_mask(__mmask64 k, __m512i A, __m512i B)

VPCMPEQB k, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-245 (PCMPEQB/PCMPEQW/PCMPEQD)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.