VPCMPEQD

VPCMPEQD compares doublewords element by element for equality. Its two encodings deliver the answer in different places:

• VEX (AVX, AVX2 for 256 bits): each doubleword of the destination vector becomes all ones where the elements are equal and zero where they differ, as with the SSE2 PCMPEQD, but into a separate register.
• EVEX (AVX512F, or AVX10.1): the destination is a mask register, one bit per element, and the optional write mask clears the bits of elements it leaves out; bits above the element count become zero. On Zen 5, vpcmpeqd k3{k4}, zmm1, zmm2 found elements 0, 5, 6, 10, 12 and 15 equal, but K4 had bits 12 and 15 clear, so K3 became 461h, its upper bits cleared.

The vector form feeds blends and masks: a[i] == b[i] ? -1 : 0 over int arrays compiles to one VPCMPEQD per vector at -O2 with -march=x86-64-v3 in GCC 14 and Clang 23, and counting matches needs no conversion, since -1 per match can be subtracted: both count a[i] == k with VPCMPEQD and VPSUBD into an accumulator.

Two idioms and AVX-512#

A register compared with itself is all ones whatever it held, and processors know it (see the page’s lines from the optimization guide): vpcmpeqd ymm0, ymm0, ymm0 is how both compilers make _mm256_set1_epi32(-1) and the all-ones operand of a vector NOT with VPXOR. The EVEX form cannot do this, as it writes a mask register; for 512 bits of ones both use VPTERNLOGD with immediate FFh.

With -march=x86-64-v4, GCC 14 switches the compare loop to zmm registers and the EVEX form, then turns the mask back into a vector with a zero-masked VMOVDQA32 of all ones; for the count it emits VPCMPD with predicate 0, the same comparison under another name. Clang 23 keeps the VEX form on ymm registers. AMD’s latency spreadsheet for Zen 5 gives the vector form one cycle, and the mask form 3, 4 and 6 cycles for xmm, ymm and zmm sources.

Zen 5’s 10 recorded cases cover all forms, with masked and unmasked EVEX compares.

In the optimization guide

What the optimization guide says about VPCMPEQD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: pcmpeqd xmm0, xmm0 and the other equality comparisons of a register with itself set every bit without waiting for the old value.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = ymm2.d[i]
    b = src3.d[i]
    ymm1.d[i] = -1 if a == b else 0
# ymm1 is zeroed from bit VL up

for i in range(VL // 32):
    k1[i] = k2[i] and zmm2.d[i] == src3.d[i]
# m32bcst: src3.d[i] is the m32 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPEQD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW

All 253 AVX instructions

More AVX2 instructions

• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPANDD
• VPANDND
• VPANDNQ
• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS

All 686 AVX10.1 instructions