Instruction
VPCMPEQQ
Compares packed quadwords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register.
VPCMPEQQ compares quadwords for equality: the VEX form writes all ones or zero per quadword into a vector, as SSE4.1’s PCMPEQQ does, whose page covers the extension it belongs to and the code compilers build without it, and the EVEX form one bit per quadword into a mask register, as VPCMPEQD’s page describes. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1, take a write mask, and, unlike the byte and word compares, a second source of one quadword broadcast from memory. On Zen 5:
{evex} vpcmpeqq k1, ymm24, ymm3set K1 to 0Ah: elements 1 and 3 were equal, and the bits above the four results were cleared.vpcmpeqq k2{k7}, zmm5, zmm5, a register against itself, copied the low byte of K7, E3h, into K2: the write mask clears the bits it leaves out rather than keeping them.vpcmpeqq ymm12, ymm6, ymm6set all of YMM12, which AMD’s Zen 5 guide lists among the ones idioms that do not wait for the old value (Section 2.9.2).
In our builds
In our builds at -O2 over fixed-size int64_t arrays with
-march=x86-64-v3, b[i] == c[i] ? -1 : 0 is one VPCMPEQQ per vector
in GCC 14 and Clang 23, and b[i] == c[i] ? 0 : b[i] adds a
VPANDN. Counting matches, n += b[i] == k, subtracts
each result with VPSUBQ: with 64-bit counters the -1
of a match cannot wrap as it would in a word counter.
With -march=x86-64-v4, GCC compares zmm registers into K1 and expands
the mask with a zero-masked VMOVDQA64 of all ones,
or of b[i] for the select, which it tests as VPCMPNEQQ, an alias of
VPCMPQ. Clang keeps the VEX form on ymm registers for
the plain result and the count, and uses VPCMPNEQQ with a masked move
for the select.
AMD’s latency spreadsheet for Zen 5 gives the VEX row 2 cycles, two per cycle on pipes FP0 and FP3, as for PCMPEQQ, and the EVEX rows, which write a mask, 3, 4 and 6 cycles for xmm, ymm and zmm sources, two per cycle.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPCMPEQQ xmm, xmm, m128
VPCMPEQQ_XMMdq_XMMdq_MEMdq | VEX.128.66.0F38.WIG 29 /r | AVX |
VPCMPEQQ xmm, xmm, xmm
VPCMPEQQ_XMMdq_XMMdq_XMMdq | VEX.128.66.0F38.WIG 29 /r | AVX |
VPCMPEQQ ymm, ymm, m256
VPCMPEQQ_YMMqq_YMMqq_MEMqq | VEX.256.66.0F38.WIG 29 /r | AVX2 |
VPCMPEQQ ymm, ymm, ymm
VPCMPEQQ_YMMqq_YMMqq_YMMqq | VEX.256.66.0F38.WIG 29 /r | AVX2 |
VPCMPEQQ k {k}, zmm, zmm
VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 | EVEX.512.66.0F38.W1 29 /r | AVX10.1 or AVX512F |
VPCMPEQQ k {k}, zmm, m512/m64bcst
VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 | EVEX.512.66.0F38.W1 29 /r | AVX10.1 or AVX512F |
VPCMPEQQ k {k}, xmm, xmm
VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 | EVEX.128.66.0F38.W1 29 /r | AVX10.1 or AVX512F + AVX512VL |
VPCMPEQQ k {k}, xmm, m128/m64bcst
VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 | EVEX.128.66.0F38.W1 29 /r | AVX10.1 or AVX512F + AVX512VL |
VPCMPEQQ k {k}, ymm, ymm
VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 | EVEX.256.66.0F38.W1 29 /r | AVX10.1 or AVX512F + AVX512VL |
VPCMPEQQ k {k}, ymm, m256/m64bcst
VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 | EVEX.256.66.0F38.W1 29 /r | AVX10.1 or AVX512F + AVX512VL |
Latency and throughput
| Model | xmm, xmm, m128 | xmm, xmm, xmm | ymm, ymm, m256 | ymm, ymm, ymm | k {k}, zmm, zmm | k {k}, zmm, m512/m64bcstk {k}, ymm, m256/m64bcst | k {k}, xmm, xmmk {k}, ymm, ymm | k {k}, xmm, m128/m64bcst |
|---|---|---|---|---|---|---|---|---|
| Sandy Bridge | 7 / 0.5p15 | 1 / 0.5p15 | ||||||
| Haswell | 7 / 0.5p15 | 1 / 0.5p15 | 8 / 0.5p15 | 1 / 0.5p15 | ||||
| Broadwell | 6 / 0.5p15 | 1 / 0.5p15 | 7 / 0.5p15 | 1 / 0.5p15 | ||||
| Skylake | 7 / 0.5p01 | 1 / 0.5p01 | 8 / 0.5p01 | 1 / 0.5p01 | ||||
| Skylake-SP, Ice Lake | 7 / 0.5p01 | 1 / 0.5p01 | 8 / 0.5p01 | 1 / 0.5p01 | 4 / 1p5 | 11 / 1p5 | 4 / 1p5 | 10 / 1p5 |
| Alder Lake | 8 / 0.5p01 | 1 / 0.5p01 | 9 / 0.5p01 | 1 / 0.5p01 | ||||
| Sapphire Rapids | 8 / 0.5p01 | 1 / 0.5p01 | 9 / 0.5p01 | 1 / 0.5p01 | 3 / 1p5 | 3 / 1p5 | 3 / 1p5 | 3 / 1p5 |
| Lunar Lake | 7 / 2V0 V1 | 1 / 0.5V0 V1 | 8 / 2.33V0 V1 | 1 / 0.5V0 V1 | ||||
| Piledriver | 7 / 1.5FPMAL | 2 / 0.5FPMAL FPU2 FPU3 | ||||||
| Zen | 8 / 0.5FPU0 FPU1 FPU3 | 1 / 0.33FPU0 FPU1 FPU3 | 8 / 0.67FPU0 FPU1 FPU3 | 1 / 0.67FPU0 FPU1 FPU3 | ||||
| Zen 2 | 8 / 0.33FPU0 FPU1 FPU3 | 1 / 0.33FPU0 FPU1 FPU3 | 8 / 0.33FPU0 FPU1 FPU3 | 1 / 0.33FPU0 FPU1 FPU3 | ||||
| Zen 3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 | ||||
| Zen 4 | 8 / 0.5FP0 FP1 FP2 FP3 | 2 / 11FP0 FP1 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.5FP0 FP1 | 1 / 0.5FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 | 1 / 0.252FP0 FP1 FP2 FP3 | 8 / 0.5FP0 FP1 FP2 FP3 |
| Jaguar | 6 / 1FPU0 FPU1 VALU0 VALU1 | 1 / 0.5FPU0 FPU1 VALU0 VALU1 | ||||||
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every quadword works alike: 2 and 4 quadwords in the xmm and ymm forms.
Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: r1, r0.
Where a bit of the write mask k2 is 0, the result bit is 0. Every quadword works alike: 2, 4 and 8 quadwords in the xmm, ymm and zmm forms. With m64bcst, one quadword from memory stands for every element of the last source.
Bit i of k1 comes from quadword i of xmm2 and xmm3. Result bits 1 to 0: r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 64):
a = ymm2.q[i]
b = src3.q[i]
ymm1.q[i] = -1 if a == b else 0
# ymm1 is zeroed from bit VL upRun on AMD Zen 5 (EPYC 9645): 4 cases.
for i in range(VL // 64):
k1[i] = k2[i] and zmm2.q[i] == src3.q[i]
# m64bcst: src3.q[i] is the m64 for every i
# the other bits of k1 are clearedRun on AMD Zen 5 (EPYC 9645): 6 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPCMPEQQ xmm, xmm, xmm/m128 VPCMPEQQ ymm, ymm, ymm/m256 | ||
xmm, ymm | explicit | write |
xmm, ymm | explicit | read |
xmm/m128, ymm/m256 | explicit | read |
VPCMPEQQ k {k}, xmm, xmm/m128/m64bcst VPCMPEQQ k {k}, ymm, ymm/m256/m64bcst VPCMPEQQ k {k}, zmm, zmm/m512/m64bcst | ||
k | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm, ymm, zmm | explicit | read |
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- VEX forms
avx-type-4- EVEX forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- EVEX forms
- write masking
- EVEX memory forms
- embedded broadcast (tuple Full); memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPCMPEQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cmpeq_epi64
__m128i _mm_cmpeq_epi64(__m128i __V1, __m128i __V2) |
|
_mm_cmpeq_epi64_mask
__mmask8 _mm_cmpeq_epi64_mask(__m128i A, __m128i B) |
|
_mm_cmpeq_epu64_mask
__mmask8 _mm_cmpeq_epu64_mask(__m128i A, __m128i B) |
|
_mm_mask_cmpeq_epi64_mask
__mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i A, __m128i B) |
|
_mm_mask_cmpeq_epu64_mask
__mmask8 _mm_mask_cmpeq_epu64_mask(__mmask8 k, __m128i A, __m128i B) |
|
_mm256_cmpeq_epi64
__m256i _mm256_cmpeq_epi64(__m256i __a, __m256i __b) |
|
_mm256_cmpeq_epi64_mask
__mmask8 _mm256_cmpeq_epi64_mask(__m256i A, __m256i B) |
|
_mm256_cmpeq_epu64_mask
__mmask8 _mm256_cmpeq_epu64_mask(__m256i A, __m256i B) |
|
_mm256_mask_cmpeq_epi64_mask
__mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i A, __m256i B) |
|
_mm256_mask_cmpeq_epu64_mask
__mmask8 _mm256_mask_cmpeq_epu64_mask(__mmask8 k, __m256i A, __m256i B) |
|
_mm512_cmpeq_epi64_mask
__mmask8 _mm512_cmpeq_epi64_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmpeq_epi64_mask
__mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i A, __m512i B) |
|
_mm512_cmpeq_epu64_mask
__mmask8 _mm512_cmpeq_epu64_mask(__m512i A, __m512i B) |
|
_mm512_mask_cmpeq_epu64_mask
__mmask8 _mm512_mask_cmpeq_epu64_mask(__mmask8 k, __m512i A, __m512i B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More AVX instructions
- VPACKUSDW
- VPACKUSWB
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDVB
- VPBLENDW
- VPCLMULQDQ
- VPCMPEQB
- VPCMPEQD
- VPCMPEQW
- VPCMPESTRI
- VPCMPESTRM
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPISTRI
- VPCMPISTRM
- VPERM2F128
- VPERMILPD
- VPERMILPS
- VPEXTRB
- VPEXTRD
- VPEXTRQ
- VPEXTRW
- VPHADDD
- VPHADDSW
- VPHADDW
- VPHMINPOSUW
More AVX2 instructions
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDD
- VPBLENDVB
- VPBLENDW
- VPBROADCASTB
- VPBROADCASTD
- VPBROADCASTQ
- VPBROADCASTW
- VPCMPEQB
- VPCMPEQD
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPERM2I128
- VPERMD
- VPERMPD
- VPERMPS
- VPERMQ
- VPGATHERDD
- VPGATHERDQ
- VPGATHERQD
- VPGATHERQQ
- VPHADDD
- VPHADDSW
- VPHADDW
- VPHSUBD
- VPHSUBSW
- VPHSUBW
More AVX10.1 instructions
- VPANDND
- VPANDNQ
- VPANDQ
- VPAVGB
- VPAVGW
- VPBLENDMB
- VPBLENDMD
- VPBLENDMQ
- VPBLENDMW
- VPBROADCASTB
- VPBROADCASTD
- VPBROADCASTMB2Q
- VPBROADCASTMW2D
- VPBROADCASTQ
- VPBROADCASTW
- VPCLMULQDQ
- VPCMPB
- VPCMPD
- VPCMPEQB
- VPCMPEQD
- VPCMPEQW
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPQ
- VPCMPUB
- VPCMPUD
- VPCMPUQ
- VPCMPUW
- VPCMPW
- VPCOMPRESSB
- VPCOMPRESSD
- VPCOMPRESSQ
- VPCOMPRESSW
- VPCONFLICTD
- VPCONFLICTQ
- VPDPBUSD
- VPDPBUSDS
- VPDPWSSD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - LLVM 23.1.2's x86 scheduling models (commit
85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-251 (PCMPEQQ)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
- Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.