Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPCMPEQQ compares quadwords for equality: the VEX form writes all ones or zero per quadword into a vector, as SSE4.1’s PCMPEQQ does, whose page covers the extension it belongs to and the code compilers build without it, and the EVEX form one bit per quadword into a mask register, as VPCMPEQD’s page describes. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1, take a write mask, and, unlike the byte and word compares, a second source of one quadword broadcast from memory. On Zen 5:

  • {evex} vpcmpeqq k1, ymm24, ymm3 set K1 to 0Ah: elements 1 and 3 were equal, and the bits above the four results were cleared.
  • vpcmpeqq k2{k7}, zmm5, zmm5, a register against itself, copied the low byte of K7, E3h, into K2: the write mask clears the bits it leaves out rather than keeping them.
  • vpcmpeqq ymm12, ymm6, ymm6 set all of YMM12, which AMD’s Zen 5 guide lists among the ones idioms that do not wait for the old value (Section 2.9.2).

In our builds

In our builds at -O2 over fixed-size int64_t arrays with -march=x86-64-v3, b[i] == c[i] ? -1 : 0 is one VPCMPEQQ per vector in GCC 14 and Clang 23, and b[i] == c[i] ? 0 : b[i] adds a VPANDN. Counting matches, n += b[i] == k, subtracts each result with VPSUBQ: with 64-bit counters the -1 of a match cannot wrap as it would in a word counter.

With -march=x86-64-v4, GCC compares zmm registers into K1 and expands the mask with a zero-masked VMOVDQA64 of all ones, or of b[i] for the select, which it tests as VPCMPNEQQ, an alias of VPCMPQ. Clang keeps the VEX form on ymm registers for the plain result and the count, and uses VPCMPNEQQ with a masked move for the select.

AMD’s latency spreadsheet for Zen 5 gives the VEX row 2 cycles, two per cycle on pipes FP0 and FP3, as for PCMPEQQ, and the EVEX rows, which write a mask, 3, 4 and 6 cycles for xmm, ymm and zmm sources, two per cycle.

Forms

Every encoding of VPCMPEQQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPCMPEQQ xmm, xmm, m128 VPCMPEQQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG 29 /rAVX
VPCMPEQQ xmm, xmm, xmm VPCMPEQQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG 29 /rAVX
VPCMPEQQ ymm, ymm, m256 VPCMPEQQ_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.WIG 29 /rAVX2
VPCMPEQQ ymm, ymm, ymm VPCMPEQQ_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.WIG 29 /rAVX2
VPCMPEQQ k {k}, zmm, zmm VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512EVEX.512.66.0F38.W1 29 /rAVX10.1 or AVX512F
VPCMPEQQ k {k}, zmm, m512/m64bcst VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F38.W1 29 /rAVX10.1 or AVX512F
VPCMPEQQ k {k}, xmm, xmm VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F38.W1 29 /rAVX10.1 or AVX512F + AVX512VL
VPCMPEQQ k {k}, xmm, m128/m64bcst VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F38.W1 29 /rAVX10.1 or AVX512F + AVX512VL
VPCMPEQQ k {k}, ymm, ymm VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512EVEX.256.66.0F38.W1 29 /rAVX10.1 or AVX512F + AVX512VL
VPCMPEQQ k {k}, ymm, m256/m64bcst VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F38.W1 29 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128xmm, xmm, xmmymm, ymm, m256ymm, ymm, ymmk {k}, zmm, zmmk {k}, zmm, m512/m64bcst
k {k}, ymm, m256/m64bcst
k {k}, xmm, xmm
k {k}, ymm, ymm
k {k}, xmm, m128/m64bcst
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p014 / 1p511 / 1p54 / 1p510 / 1p5
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p013 / 1p53 / 1p53 / 1p53 / 1p5
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1
Zen 48 / 0.5FP0 FP1 FP2 FP32 / 11FP0 FP18 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP11 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.252FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2091; AMD 58455, row 1248).
  2. Zen 4 model, xmm form: AMD's spreadsheets give latency 3 for Zen 4 and Zen 5 (AMD 57647, row 2086; AMD 58455, row 443).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.VEX forms
VPCMPEQQ: element by elementResult quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: r1, r0.01xmm2ar0r1xmm101xmm3or m128b

Every quadword works alike: 2 and 4 quadwords in the xmm and ymm forms.

Result quadword i comes from quadword i of xmm2 and xmm3. Result quadwords 1 to 0: r1, r0.

To a mask: each quadword of the sources sets one bit of k1, bit i for quadword i.EVEX forms
VPCMPEQQ: a bit of k1 per elementBit i of k1 comes from quadword i of xmm2 and xmm3. Result bits 1 to 0: r1, r0.11k2r0r1k101xmm3or m128b

Where a bit of the write mask k2 is 0, the result bit is 0. Every quadword works alike: 2, 4 and 8 quadwords in the xmm, ymm and zmm forms. With m64bcst, one quadword from memory stands for every element of the last source.

Bit i of k1 comes from quadword i of xmm2 and xmm3. Result bits 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VEX forms
for i in range(VL // 64):
    a = ymm2.q[i]
    b = src3.q[i]
    ymm1.q[i] = -1 if a == b else 0
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

EVEX forms
for i in range(VL // 64):
    k1[i] = k2[i] and zmm2.q[i] == src3.q[i]
# m64bcst: src3.q[i] is the m64 for every i
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPCMPEQQ xmm, xmm, xmm/m128 VPCMPEQQ ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPCMPEQQ k {k}, xmm, xmm/m128/m64bcst VPCMPEQQ k {k}, ymm, ymm/m256/m64bcst VPCMPEQQ k {k}, zmm, zmm/m512/m64bcst
kexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPEQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmpeq_epi64 __m128i _mm_cmpeq_epi64(__m128i __V1, __m128i __V2)

VPCMPEQQ xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_cmpeq_epi64_mask __mmask8 _mm_cmpeq_epi64_mask(__m128i A, __m128i B)

VPCMPEQQ k, xmm, xmm EVEX.128 -mavx512vl

_mm_cmpeq_epu64_mask __mmask8 _mm_cmpeq_epu64_mask(__m128i A, __m128i B)

VPCMPEQQ k, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_cmpeq_epi64_mask __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPEQQ k {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_cmpeq_epu64_mask __mmask8 _mm_mask_cmpeq_epu64_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPEQQ k {k}, xmm, xmm EVEX.128 -mavx512vl

_mm256_cmpeq_epi64 __m256i _mm256_cmpeq_epi64(__m256i __a, __m256i __b)

VPCMPEQQ ymm, ymm, ymm VEX.256 -mavx2

_mm256_cmpeq_epi64_mask __mmask8 _mm256_cmpeq_epi64_mask(__m256i A, __m256i B)

VPCMPEQQ k, ymm, ymm EVEX.256 -mavx512vl

_mm256_cmpeq_epu64_mask __mmask8 _mm256_cmpeq_epu64_mask(__m256i A, __m256i B)

VPCMPEQQ k, ymm, ymm EVEX.256 -mavx512vl

_mm256_mask_cmpeq_epi64_mask __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i A, __m256i B)

VPCMPEQQ k {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_mask_cmpeq_epu64_mask __mmask8 _mm256_mask_cmpeq_epu64_mask(__mmask8 k, __m256i A, __m256i B)

VPCMPEQQ k {k}, ymm, ymm EVEX.256 -mavx512vl

_mm512_cmpeq_epi64_mask __mmask8 _mm512_cmpeq_epi64_mask(__m512i A, __m512i B)

VPCMPEQQ k, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_cmpeq_epi64_mask __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i A, __m512i B)

VPCMPEQQ k, zmm, zmm EVEX.512 -mavx512f

_mm512_cmpeq_epu64_mask __mmask8 _mm512_cmpeq_epu64_mask(__m512i A, __m512i B)

VPCMPEQQ k, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_cmpeq_epu64_mask __mmask8 _mm512_mask_cmpeq_epu64_mask(__mmask8 k, __m512i A, __m512i B)

VPCMPEQQ k, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-251 (PCMPEQQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.