Extensions
Forms
4 (4 VEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPCMPESTRM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPCMPESTRM xmm, m128, imm8 VPCMPESTRM_XMMdq_MEMdq_IMMbVEX.128.66.0F3A.W0 60 /r ibAVX
VPCMPESTRM xmm, xmm, imm8 VPCMPESTRM_XMMdq_XMMdq_IMMbVEX.128.66.0F3A.W0 60 /r ibAVX
VPCMPESTRM xmm, m128, imm8 64-bit mode only VPCMPESTRM64_XMMdq_MEMdq_IMMbVEX.128.66.0F3A.W1 60 /r ibAVX
VPCMPESTRM xmm, xmm, imm8 64-bit mode only VPCMPESTRM64_XMMdq_XMMdq_IMMbVEX.128.66.0F3A.W1 60 /r ibAVX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

All forms but the forms only in 64-bit mode
n = 8 if imm8 & 1 else 16  # words, bytes
w = 128 // n               # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0  # signed
# the lengths: |EAX| and |EDX|, at most n,
# the count of imm8[0] (not of imm8[3])
la = min(abs(signed(eax)), n)
lb = min(abs(signed(edx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n):     # bit j: src2's
    y = (b >> w * j & m ^ k) - k  # element j
    bit = 0
    if agg == 0:       # equal any: y is
        for i in range(la):  # in xmm1
            x = (a >> w * i & m ^ k) - k
            if j < lb and x == y:
                bit = 1
    elif agg == 1:     # ranges: y is in
        for i in range(0, la - 1, 2):
            t = w * i  # a pair's range
            lo = (a >> t & m ^ k) - k
            hi = (a >> t + w & m ^ k) - k
            if j < lb and lo <= y <= hi:
                bit = 1
    elif agg == 2:     # equal each
        x = (a >> w * j & m ^ k) - k
        if j < la and j < lb:
            bit = x == y
        else:          # 1 past both ends
            bit = j >= la and j >= lb
    else:              # equal ordered: xmm1
        bit = 1        # from element j on;
        # what would fall past the end of the
        # register matches, and an empty xmm1
        # everywhere, as in Intel's manual
        # (AMD's clears these bits)
        for i in range(min(la, n - j)):
            x = (a >> w * i & m ^ k) - k
            u = j + i
            z = (b >> w * u & m ^ k) - k
            if u >= lb or x != z:
                bit = 0
    r |= bit << j
p = imm8 >> 4 & 3
if p == 1:             # negated
    r ^= (1 << n) - 1
elif p == 3:           # negated within src2
    r ^= (1 << lb) - 1
# imm8[6]: each bit made an element of ones,
# words where imm8[0] is set (whatever
# imm8[1], which Intel's table names)
if imm8 & 0x40:
    v = 0
    for j in range(n):
        if r >> j & 1:
            v |= m << w * j
    xmm0.write(v)
else:
    xmm0.write(r)      # the bits alone
cf = r != 0
zf = lb < n            # src2 is short
sf = la < n            # xmm1 is short
of = r & 1
af = pf = 0
# xmm0 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Forms only in 64-bit mode
n = 8 if imm8 & 1 else 16  # words, bytes
w = 128 // n               # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0  # signed
# the lengths: |RAX| and |RDX|, read whole
# with VEX.W1 (which AMD's manual marks as
# ignored), at most n, the count of imm8[0]
la = min(abs(signed(rax)), n)
lb = min(abs(signed(rdx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n):     # bit j: src2's
    y = (b >> w * j & m ^ k) - k  # element j
    bit = 0
    if agg == 0:       # equal any: y is
        for i in range(la):  # in xmm1
            x = (a >> w * i & m ^ k) - k
            if j < lb and x == y:
                bit = 1
    elif agg == 1:     # ranges: y is in
        for i in range(0, la - 1, 2):
            t = w * i  # a pair's range
            lo = (a >> t & m ^ k) - k
            hi = (a >> t + w & m ^ k) - k
            if j < lb and lo <= y <= hi:
                bit = 1
    elif agg == 2:     # equal each
        x = (a >> w * j & m ^ k) - k
        if j < la and j < lb:
            bit = x == y
        else:          # 1 past both ends
            bit = j >= la and j >= lb
    else:              # equal ordered: xmm1
        bit = 1        # from element j on;
        # what would fall past the end of the
        # register matches, and an empty xmm1
        # everywhere, as in Intel's manual
        # (AMD's clears these bits)
        for i in range(min(la, n - j)):
            x = (a >> w * i & m ^ k) - k
            u = j + i
            z = (b >> w * u & m ^ k) - k
            if u >= lb or x != z:
                bit = 0
    r |= bit << j
p = imm8 >> 4 & 3
if p == 1:             # negated
    r ^= (1 << n) - 1
elif p == 3:           # negated within src2
    r ^= (1 << lb) - 1
# imm8[6]: each bit made an element of ones,
# words where imm8[0] is set (whatever
# imm8[1], which Intel's table names)
if imm8 & 0x40:
    v = 0
    for j in range(n):
        if r >> j & 1:
            v |= m << w * j
    xmm0.write(v)
else:
    xmm0.write(r)      # the bits alone
cf = r != 0
zf = lb < n            # src2 is short
sf = la < n            # xmm1 is short
of = r & 1
af = pf = 0
# xmm0 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPCMPESTRM xmm, xmm/m128, imm8
xmmexplicitread
xmm/m128explicitread
imm8explicitread
rAXimplicitread
rDXimplicitread
XMM0implicitwrite
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
MMM00M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPESTRM, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmpestrm __m128i _mm_cmpestrm(__m128i A, int LA, __m128i B, int LB, const int M)

VPCMPESTRM xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

More AVX instructions

All 253 AVX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-256 (PCMPESTRM)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.