Instruction
VPCMPESTRM
Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with VEX.W1) as an immediate says, returning a mask in XMM0.
- Extensions
- Forms
- 4 (4 VEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPCMPESTRM xmm, m128, imm8
VPCMPESTRM_XMMdq_MEMdq_IMMb | VEX.128.66.0F3A.W0 60 /r ib | AVX |
VPCMPESTRM xmm, xmm, imm8
VPCMPESTRM_XMMdq_XMMdq_IMMb | VEX.128.66.0F3A.W0 60 /r ib | AVX |
VPCMPESTRM xmm, m128, imm8 64-bit mode only
VPCMPESTRM64_XMMdq_MEMdq_IMMb | VEX.128.66.0F3A.W1 60 /r ib | AVX |
VPCMPESTRM xmm, xmm, imm8 64-bit mode only
VPCMPESTRM64_XMMdq_XMMdq_IMMb | VEX.128.66.0F3A.W1 60 /r ib | AVX |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
n = 8 if imm8 & 1 else 16 # words, bytes
w = 128 // n # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0 # signed
# the lengths: |EAX| and |EDX|, at most n,
# the count of imm8[0] (not of imm8[3])
la = min(abs(signed(eax)), n)
lb = min(abs(signed(edx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n): # bit j: src2's
y = (b >> w * j & m ^ k) - k # element j
bit = 0
if agg == 0: # equal any: y is
for i in range(la): # in xmm1
x = (a >> w * i & m ^ k) - k
if j < lb and x == y:
bit = 1
elif agg == 1: # ranges: y is in
for i in range(0, la - 1, 2):
t = w * i # a pair's range
lo = (a >> t & m ^ k) - k
hi = (a >> t + w & m ^ k) - k
if j < lb and lo <= y <= hi:
bit = 1
elif agg == 2: # equal each
x = (a >> w * j & m ^ k) - k
if j < la and j < lb:
bit = x == y
else: # 1 past both ends
bit = j >= la and j >= lb
else: # equal ordered: xmm1
bit = 1 # from element j on;
# what would fall past the end of the
# register matches, and an empty xmm1
# everywhere, as in Intel's manual
# (AMD's clears these bits)
for i in range(min(la, n - j)):
x = (a >> w * i & m ^ k) - k
u = j + i
z = (b >> w * u & m ^ k) - k
if u >= lb or x != z:
bit = 0
r |= bit << j
p = imm8 >> 4 & 3
if p == 1: # negated
r ^= (1 << n) - 1
elif p == 3: # negated within src2
r ^= (1 << lb) - 1
# imm8[6]: each bit made an element of ones,
# words where imm8[0] is set (whatever
# imm8[1], which Intel's table names)
if imm8 & 0x40:
v = 0
for j in range(n):
if r >> j & 1:
v |= m << w * j
xmm0.write(v)
else:
xmm0.write(r) # the bits alone
cf = r != 0
zf = lb < n # src2 is short
sf = la < n # xmm1 is short
of = r & 1
af = pf = 0
# xmm0 is zeroed from bit 128 upRun on AMD Zen 5 (EPYC 9645): 4 cases.
n = 8 if imm8 & 1 else 16 # words, bytes
w = 128 // n # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0 # signed
# the lengths: |RAX| and |RDX|, read whole
# with VEX.W1 (which AMD's manual marks as
# ignored), at most n, the count of imm8[0]
la = min(abs(signed(rax)), n)
lb = min(abs(signed(rdx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n): # bit j: src2's
y = (b >> w * j & m ^ k) - k # element j
bit = 0
if agg == 0: # equal any: y is
for i in range(la): # in xmm1
x = (a >> w * i & m ^ k) - k
if j < lb and x == y:
bit = 1
elif agg == 1: # ranges: y is in
for i in range(0, la - 1, 2):
t = w * i # a pair's range
lo = (a >> t & m ^ k) - k
hi = (a >> t + w & m ^ k) - k
if j < lb and lo <= y <= hi:
bit = 1
elif agg == 2: # equal each
x = (a >> w * j & m ^ k) - k
if j < la and j < lb:
bit = x == y
else: # 1 past both ends
bit = j >= la and j >= lb
else: # equal ordered: xmm1
bit = 1 # from element j on;
# what would fall past the end of the
# register matches, and an empty xmm1
# everywhere, as in Intel's manual
# (AMD's clears these bits)
for i in range(min(la, n - j)):
x = (a >> w * i & m ^ k) - k
u = j + i
z = (b >> w * u & m ^ k) - k
if u >= lb or x != z:
bit = 0
r |= bit << j
p = imm8 >> 4 & 3
if p == 1: # negated
r ^= (1 << n) - 1
elif p == 3: # negated within src2
r ^= (1 << lb) - 1
# imm8[6]: each bit made an element of ones,
# words where imm8[0] is set (whatever
# imm8[1], which Intel's table names)
if imm8 & 0x40:
v = 0
for j in range(n):
if r >> j & 1:
v |= m << w * j
xmm0.write(v)
else:
xmm0.write(r) # the bits alone
cf = r != 0
zf = lb < n # src2 is short
sf = la < n # xmm1 is short
of = r & 1
af = pf = 0
# xmm0 is zeroed from bit 128 upRun on AMD Zen 5 (EPYC 9645): 3 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VPCMPESTRM xmm, xmm/m128, imm8 | ||
xmm | explicit | read |
xmm/m128 | explicit | read |
imm8 | explicit | read |
rAX | implicit | read |
rDX | implicit | read |
XMM0 | implicit | write |
RFLAGS | implicit | write |
Flags
| OF | SF | ZF | AF | PF | CF |
|---|---|---|---|---|---|
| All forms | |||||
| M | M | M | 0 | 0 | M |
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
avx-type-4
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPCMPESTRM, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cmpestrm
__m128i _mm_cmpestrm(__m128i A, int LA, __m128i B, int LB, const int M) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX | AVX | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 |
More AVX instructions
- VPADDD
- VPADDQ
- VPADDSB
- VPADDSW
- VPADDUSB
- VPADDUSW
- VPADDW
- VPALIGNR
- VPAND
- VPANDN
- VPAVGB
- VPAVGW
- VPBLENDVB
- VPBLENDW
- VPCLMULQDQ
- VPCMPEQB
- VPCMPEQD
- VPCMPEQQ
- VPCMPEQW
- VPCMPESTRI
- VPCMPGTB
- VPCMPGTD
- VPCMPGTQ
- VPCMPGTW
- VPCMPISTRI
- VPCMPISTRM
- VPERM2F128
- VPERMILPD
- VPERMILPS
- VPEXTRB
- VPEXTRD
- VPEXTRQ
- VPEXTRW
- VPHADDD
- VPHADDSW
- VPHADDW
- VPHMINPOSUW
- VPHSUBD
- VPHSUBSW
- VPHSUBW
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-256 (PCMPESTRM)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.