VPCMPGTB

VPCMPGTB compares bytes as signed integers and marks those where the first source is the greater: the VEX and EVEX form of SSE2’s PCMPGTB, whose page builds the other orderings from it. The VEX form writes FFh or 00h per byte into a vector, the EVEX form one bit per byte into a mask register, the split VPCMPGTD’s page describes, with up to 64 bits for a zmm compare. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1 and take a write mask, but no broadcast.

On Zen 5, vpcmpgtb xmm1, xmm2, xmmword ptr [mem] found 7Fh greater than FFh and 00h greater than 80h, but not 80h greater than FFh, -128 against -1. {evex} vpcmpgtb k4, ymm7, ymm12 set K4 to 872521C9h, its upper 32 bits cleared, and vpcmpgtb k6{k4}, zmm7, zmmword ptr [mem] filled all 64 bits of K6 with 42002A0148486040h, within the bits K4 selects. vpcmpgtb xmm12, xmm6, xmm6 gave zeros, and AMD’s Zen 5 guide lists that use among the zeroing idioms (Section 2.9.2).

Bytes in compiled code#

Bytes have no arithmetic shift, so a sign mask is a compare. In our builds at -O2 over fixed-size int8_t arrays with -march=x86-64-v3, b[i] < 0 ? -1 : 0 is VPCMPGTB of a zeroed register against the data in GCC 14 and Clang 23, and b[i] > c[i] ? -1 : 0 one VPCMPGTB per vector. With -march=x86-64-v4 Clang keeps both, while GCC compares zmm registers into K1, with VPCMPLTB and VPCMPNLEB, aliases of VPCMPB, and expands the mask with a zero-masked VMOVDQU8.

A select, b[i] > c[i] ? b[i] : c[i] + 1, is VPCMPGTB and VPBLENDVB at -v3. At -v4 Clang compares into mask registers and merges b into the sums with VMOVDQU8, while GCC adds 1 only under the mask of VPCMPLEB, with a merging VPADDB.

AMD’s latency spreadsheet for Zen 5 gives the VEX row one cycle, four per cycle, and the EVEX rows, which write a mask, 3, 4 and 6 cycles for xmm, ymm and zmm sources, two per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    sa = ymm2.sb[i]
    sb = src3.sb[i]
    ymm1.b[i] = -1 if sa > sb else 0
# ymm1 is zeroed from bit VL up

for i in range(VL // 8):
    sa = zmm2.sb[i]
    sb = src3.sb[i]
    k1[i] = k2[i] and sa > sb
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPGTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB

All 253 AVX instructions

More AVX2 instructions

• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPANDQ
• VPAVGB
• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB

All 686 AVX10.1 instructions