x86-64.net

Instruction

VPCMPGTD

Tests packed signed doublewords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPCMPGTD compares doublewords as signed integers and marks the elements where the first source is greater than the second. Like VPCMPEQD, whose page describes the two places the answer can go, the VEX form writes all ones or zero per element into a vector and the EVEX form one bit per element into a mask register. It is the VEX and EVEX form of SSE2’s PCMPGTD.

Signed, and only greater-than

The comparison is signed: on Zen 5, vpcmpgtd xmm1, xmm2, xmm3 found 0 greater than 80000000h, which is -2147483648. The other orderings take more:

  • Less-than swaps the operands.
  • Greater or equal is the inverse of less-than: a NOT, which AVX2 makes with VPXOR against all ones, or a select with its two inputs swapped.
  • Unsigned needs a detour. For a[i] = b[i] > c[i] ? -1 : 0 over unsigned, GCC 14 at -O2 with -march=x86-64-v3 subtracts 80000000h from both sides, which flips their sign bits, and compares signed; Clang 23 takes VPMINUD, compares the minimum with VPCMPEQD and inverts the result with VPXOR.

The same loop over int is one VPCMPGTD per vector in both, and b[i] > c[i] ? b[i] : 0 adds a VPAND.

AVX-512

With -march=x86-64-v4, the compilers go through mask registers. Clang compiles the selecting loop to the EVEX VPCMPGTD into K1 and a zero-masked VMOVDQA32, and the unsigned one to VPCMPNLEUD, an alias of VPCMPUD, while the plain int loop keeps the VEX form; GCC uses VPCMPD and VPCMPUD with an immediate throughout.

A register is never greater than itself, and AMD’s Zen 5 guide lists VPCMPGTD with the same register twice among the zeroing idioms, which take no cycle (Section 2.9.2). Zen 5’s 10 recorded cases cover every form; in the EVEX ones the write mask cleared the bits it left out, as with vpcmpgtd k3{k1}, xmm1, xmm2, which found elements 0 and 3 greater but wrote 0, the low four bits of K1 being clear.

Forms

Every encoding of VPCMPGTD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPCMPGTD xmm, xmm, m128 VPCMPGTD_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 66 /rAVX
VPCMPGTD xmm, xmm, xmm VPCMPGTD_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 66 /rAVX
VPCMPGTD ymm, ymm, m256 VPCMPGTD_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 66 /rAVX2
VPCMPGTD ymm, ymm, ymm VPCMPGTD_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 66 /rAVX2
VPCMPGTD k {k}, zmm, zmm VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512EVEX.512.66.0F.W0 66 /rAVX10.1 or AVX512F
VPCMPGTD k {k}, zmm, m512/m32bcst VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512EVEX.512.66.0F.W0 66 /rAVX10.1 or AVX512F
VPCMPGTD k {k}, xmm, xmm VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512EVEX.128.66.0F.W0 66 /rAVX10.1 or AVX512F + AVX512VL
VPCMPGTD k {k}, xmm, m128/m32bcst VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512EVEX.128.66.0F.W0 66 /rAVX10.1 or AVX512F + AVX512VL
VPCMPGTD k {k}, ymm, ymm VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512EVEX.256.66.0F.W0 66 /rAVX10.1 or AVX512F + AVX512VL
VPCMPGTD k {k}, ymm, m256/m32bcst VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512EVEX.256.66.0F.W0 66 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128xmm, xmm, xmmymm, ymm, m256ymm, ymm, ymmk {k}, zmm, zmmno mask
k {k}, xmm, xmm
k {k}, ymm, ymm		k {k}, zmm, zmmwith a maskk {k}, zmm, m512/m32bcst
k {k}, ymm, m256/m32bcst		k {k}, xmm, m128/m32bcst
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p014 / 1p54 / 1p511 / 1p510 / 1p5
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p013 / 1p53 / 1p53 / 1p53 / 1p5
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP3
Zen 48 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.251FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model, xmm form: AMD's spreadsheets give latency 3 for Zen 4 and Zen 5 (AMD 57647, row 2112; AMD 58455, row 216).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.VEX forms
VPCMPGTD: element by elementResult doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: r3, r2, r1, r0.0123xmm2ar0r1r2r3xmm10123xmm3or m128b

Every doubleword works alike: 4 and 8 doublewords in the xmm and ymm forms.

Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: r3, r2, r1, r0.

To a mask: each doubleword of the sources sets one bit of k1, bit i for doubleword i.EVEX forms
VPCMPGTD: a bit of k1 per elementBit i of k1 comes from doubleword i of xmm2 and xmm3. Result bits 3 to 0: r3, 0 (bit 2 of k2 is 0), r1, r0.1110k2r0r1r30k10123xmm3or m128b

Where a bit of the write mask k2 is 0, the result bit is 0. Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. With m32bcst, one doubleword from memory stands for every element of the last source.

Bit i of k1 comes from doubleword i of xmm2 and xmm3. Result bits 3 to 0: r3, 0 (bit 2 of k2 is 0), r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VEX forms
for i in range(VL // 32):
    sa = ymm2.sd[i]
    sb = src3.sd[i]
    ymm1.d[i] = -1 if sa > sb else 0
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

EVEX forms
for i in range(VL // 32):
    sa = zmm2.sd[i]
    sb = src3.sd[i]
    k1[i] = k2[i] and sa > sb
# m32bcst: src3.d[i] is the m32 for every i
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPCMPGTD xmm, xmm, xmm/m128 VPCMPGTD ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPCMPGTD k {k}, xmm, xmm/m128/m32bcst VPCMPGTD k {k}, ymm, ymm/m256/m32bcst VPCMPGTD k {k}, zmm, zmm/m512/m32bcst
kexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPGTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cmpgt_epi32 __m128i _mm_cmpgt_epi32(__m128i __a, __m128i __b)

VPCMPGTD xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_cmpgt_epi32_mask __mmask8 _mm_cmpgt_epi32_mask(__m128i A, __m128i B)

VPCMPGTD k, xmm, xmm EVEX.128 -mavx512vl

_mm_cmplt_epi32 __m128i _mm_cmplt_epi32(__m128i __a, __m128i __b)

VPCMPGTD xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_cmplt_epi32_mask __mmask8 _mm_cmplt_epi32_mask(__m128i A, __m128i B)

VPCMPGTD k, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_cmpgt_epi32_mask __mmask8 _mm_mask_cmpgt_epi32_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPGTD k {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_cmplt_epi32_mask __mmask8 _mm_mask_cmplt_epi32_mask(__mmask8 k, __m128i A, __m128i B)

VPCMPGTD k {k}, xmm, xmm EVEX.128 -mavx512vl

_mm256_cmpgt_epi32 __m256i _mm256_cmpgt_epi32(__m256i __a, __m256i __b)

VPCMPGTD ymm, ymm, ymm VEX.256 -mavx2

_mm256_cmpgt_epi32_mask __mmask8 _mm256_cmpgt_epi32_mask(__m256i A, __m256i B)

VPCMPGTD k, ymm, ymm EVEX.256 -mavx512vl

_mm256_mask_cmpgt_epi32_mask __mmask8 _mm256_mask_cmpgt_epi32_mask(__mmask8 k, __m256i A, __m256i B)

VPCMPGTD k, ymm, ymm EVEX.256 -mavx512vl

_mm256_cmplt_epi32_mask __mmask8 _mm256_cmplt_epi32_mask(__m256i A, __m256i B)

VPCMPGTD k, ymm, ymm EVEX.256 -mavx512vl

_mm256_mask_cmplt_epi32_mask __mmask8 _mm256_mask_cmplt_epi32_mask(__mmask8 k, __m256i A, __m256i B)

VPCMPGTD k, ymm, ymm EVEX.256 -mavx512vl

_mm512_cmpgt_epi32_mask __mmask16 _mm512_cmpgt_epi32_mask(__m512i A, __m512i B)

VPCMPGTD k, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_cmpgt_epi32_mask __mmask16 _mm512_mask_cmpgt_epi32_mask(__mmask16 k, __m512i A, __m512i B)

VPCMPGTD k, zmm, zmm EVEX.512 -mavx512f

_mm512_cmplt_epi32_mask __mmask16 _mm512_cmplt_epi32_mask(__m512i A, __m512i B)

VPCMPGTD k, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_cmplt_epi32_mask __mmask16 _mm512_mask_cmplt_epi32_mask(__mmask16 k, __m512i A, __m512i B)

VPCMPGTD k, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-258 (PCMPGTB/PCMPGTW/PCMPGTD)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.