VPCMPGTQ

VPCMPGTQ compares quadwords as signed integers and marks the elements where the first source is greater: the VEX form with all ones or zero per element in a vector, as SSE4.2’s PCMPGTQ does, whose page covers the maximum and the unsigned order built from it, and the EVEX form with one bit per element in a mask register, as VPCMPGTD’s page describes. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1, take a write mask and accept a quadword broadcast from memory. On Zen 5, vpcmpgtq ymm4, ymm4, ymmword ptr [mem] found 7FFFFFFFFFFFFFFFh greater than -1 but 8000000000000000h greater neither than 1 nor than -1, and in vpcmpgtq k3{k6}, zmm7, zmm12 elements 0, 2 and 5 were greater but K3 became 24h, the result ANDed with the low byte of K6, A4h.

What AVX2 lacks#

AVX2 has no arithmetic right shift, absolute value, minimum or maximum of quadwords, and VPCMPGTQ stands in for each. In our builds at -O2 over fixed-size int64_t arrays with -march=x86-64-v3, GCC 14 and Clang 23 compute b[i] >> 63 as VPCMPGTQ of a zeroed register against b[i], the sign spread over the quadword; GCC builds b[i] < 0 ? -b[i] : b[i] from that mask with VPXOR and VPSUBQ, where Clang subtracts from zero and selects by the sign bit with VBLENDVPD; and the maximum is VPCMPGTQ and a blend, VPBLENDVB in GCC and VBLENDVPD in Clang. With -march=x86-64-v4 the same loops become VPSRAQ, VPABSQ and VPMAXSQ, and the unsigned compare, which at -v3 first moves both sides down by 8000000000000000h, becomes VPCMPNLEUQ, an alias of VPCMPUQ.

A register is never greater than itself, and AMD’s Zen 5 guide lists VPCMPGTQ with one register twice among the zeroing idioms, which take no cycle (Section 2.9.2). Its latency spreadsheet gives the VEX row 2 cycles, two per cycle on pipes FP0 and FP3, and the EVEX rows 3, 4 and 6 cycles for xmm, ymm and zmm sources, two per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    sa = ymm2.sq[i]
    sb = src3.sq[i]
    ymm1.q[i] = -1 if sa > sb else 0
# ymm1 is zeroed from bit VL up

for i in range(VL // 64):
    sa = zmm2.sq[i]
    sb = src3.sq[i]
    k1[i] = k2[i] and sa > sb
# m64bcst: src3.q[i] is the m64 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPGTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTB
• VPCMPGTD
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ

All 253 AVX instructions

More AVX2 instructions

• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VPAVGW
• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTW
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B

All 686 AVX10.1 instructions