VPCMPGTW

VPCMPGTW compares words as signed integers and marks those where the first source is the greater: the VEX form with FFFFh or 0000h per word in a vector, as SSE2’s PCMPGTW does, whose page covers sign masks and unsigned words, and the EVEX form with one bit per word in a mask register, the split VPCMPGTD’s page describes. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1 and take a write mask, but no broadcast.

On Zen 5, vpcmpgtw xmm0, xmm13, xmm9 gave 0000h for 8000h against 7FFFh and for FFFFh against 0001h, and vpcmpgtw k1{k2}, xmm9, xmmword ptr [mem] found words 0, 1, 2 and 7 greater, of which K2 selected 0 and 7, so K1 became 81h. No register is greater than itself: vpcmpgtw ymm4, ymm4, ymm4 gave zeros and {evex} vpcmpgtw k4, ymm5, ymm5 cleared K4. AMD’s Zen 5 guide lists VPCMPGTW with one register twice among the zeroing idioms, which take no cycle (Section 2.9.2).

In compiled code#

In our builds at -O2 over fixed-size int16_t arrays, b[i] > c[i] ? -1 : 0 is one VPCMPGTW per vector in GCC 14 and Clang 23 with -march=x86-64-v3, and b[i] > c[i] ? b[i] : 0 adds a VPAND. With -march=x86-64-v4 the compares move to mask registers:

• Selects. For the second loop, GCC writes VPCMPNLEW, an alias of VPCMPW, into K1 on zmm registers, and Clang the EVEX VPCMPGTW on ymm registers, both followed by a zero-masked VMOVDQU16; for the first, Clang keeps the VEX form.
• Conditional stores. if (b[i] > c[i]) a[i] = c[i] stays scalar in GCC at -v3, and Clang stores word by word with VPEXTRW under branches; at -v4 both store under the compare’s mask with VMOVDQU16, Clang writing the compare as VPCMPLTW with its operands swapped.

AMD’s latency spreadsheet for Zen 5 gives the VEX row one cycle, four per cycle, and the EVEX rows, which write a mask, 3, 4 and 6 cycles for xmm, ymm and zmm sources, two per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    sa = ymm2.sw[i]
    sb = src3.sw[i]
    ymm1.w[i] = -1 if sa > sb else 0
# ymm1 is zeroed from bit VL up

for i in range(VL // 16):
    sa = zmm2.sw[i]
    sb = src3.sw[i]
    k1[i] = k2[i] and sa > sb
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPGTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDVB
• VPBLENDW
• VPCLMULQDQ
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPESTRI
• VPCMPESTRM
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW

All 253 AVX instructions

More AVX2 instructions

• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB

All 138 AVX2 instructions

More AVX10.1 instructions

• VPBLENDMB
• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPQ
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D

All 686 AVX10.1 instructions