VPCMPQ

VPCMPQ compares 2, 4 or 8 pairs of signed quadwords and writes one bit per pair to a mask register. The tests chosen by the immediate, the write mask that clears rather than merges, and the compilers’ choice between this opcode and the shorter VPCMPEQ and VPCMPGT forms are as on the VPCMPD page; VPCMPUQ is the unsigned twin. Only bits 2:0 of the immediate count. On Zen 5, vpcmpq k4{k7}, zmm17, zmmword ptr [mem], 0xa tested less or equal, as 2 does: of the five elements K7 selected, it set the bits of the one equal pair and the two smaller ones, and element 2, smaller as well, stayed 0 because K7 left it out. The bits above the element count are cleared: vpcmpq k4, ymm9, ymm9, 0x7, always true, gave 0Fh.

Quadword compares before AVX-512#

SSE came late to 64-bit compares: equality with SSE4.1’s PCMPEQQ and signed greater-than with SSE4.2’s PCMPGTQ, and nothing unsigned. With -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile a[i] < b[i] over uint64_t by flipping the sign bit of both operands, GCC with a VPSUBQ of 8000000000000000h and Clang with a VPXOR, before VPCMPGTQ. With -march=x86-64-v4 the same loop becomes VPCMPUQ into a mask register, and Clang widens the mask back to quadwords with VPMOVM2Q.

For the signed a[i] <= b[i] ? 1 : 0, GCC at x86-64-v4 emits VPCMPQ with predicate 5, not less, and the operands swapped, on ZMM registers, followed by a zero-masked VMOVDQA64; Clang keeps the VEX VPCMPGTQ and a VPANDN on YMM registers. A select of the smaller element, a[i] < b[i] ? a[i] : b[i], needs no compare at all there: AVX-512 added VPMINSQ, which both compilers use, where AVX2 code compares and blends (with VPBLENDVB in GCC and VBLENDVPD in Clang).

AMD’s latency spreadsheet for Zen 5 lists VPCMPQ like VPCMPD: 3, 4 and 6 cycles for XMM, YMM and ZMM sources.

In the optimization guide

What the optimization guide says about VPCMPQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: An AVX-512 compare that writes a mask register, such as VPCMPD, takes 3, 4 or 5 cycles for 128, 256 or 512 bits, where the older compares into a vector register take one cycle for integers and two for floats. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    sa = zmm2.sq[i]
    sb = src3.sq[i]
    k1[i] = k2[i] and compare(imm8, sa, sb)
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 false, 4 !=, 5 >=, 6 >, 7 true
# m64bcst: src3.q[i] is the m64 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBLENDMD
• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPUB
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD

All 686 AVX10.1 instructions