VPCMPUB

VPCMPUB compares 16, 32 or 64 pairs of bytes as unsigned numbers and writes one bit per pair to a mask register. The immediate picks the test as for VPCMPD: 0 equal, 1 less, 2 less or equal, 4 not equal, 5 greater or equal, 6 greater, and 3 and 7 the constants false and true. VPCMPB is the signed twin. Both need AVX512BW (or AVX10.1), and unlike the doubleword compares they take no broadcast operand.

SSE and AVX have no unsigned ordered compare of bytes (only AMD’s XOP had one, VPCOMUB): PCMPGTB is signed, and an unsigned < takes two to four instructions, as PMINUB shows. With -march=x86-64-v4, Clang 23 at -O2 compiles a < b on vectors of uint8_t to VPCMPUB (printed vpcmpltub) and VPMOVM2B to turn the mask back into bytes; GCC 14 keeps VPMINUB and VPCMPEQB, with a VPANDNQ against all ones as the NOT.

Range tests#

Unsigned order turns a test for a range into one compare: c - 'a', taken as an unsigned byte, is below 26 exactly for the lowercase letters, since the subtraction wraps every byte below 'a' around to a large value. For a loop that upper-cases a buffer with that test, Clang at -march=x86-64-v4 emits per 32 bytes a VPADDB of -97, VPCMPUB against 26, a VPADDB of -32 and a VMOVDQU8 store masked by the compare, which writes only the changed bytes; GCC keeps the loop scalar at -O2. Written with intrinsics, _mm512_cmplt_epu8_mask after _mm512_sub_epi8, both compilers emit VPCMPUB.

The 64-bit mask#

A ZMM compare of bytes fills 64 mask bits, so moving the result to a general-purpose register takes KMOVQ, also AVX512BW: both compilers return _mm512_cmplt_epu8_mask(a, b) with kmovq rax, k0, and TZCNT of that finds the first byte that passed, as PMOVMSKB does for 16 bytes. AMD’s Zen 5 guide lists the same latencies as for VPCMPD: 3, 4 and 6 cycles for XMM, YMM and ZMM.

In the optimization guide

What the optimization guide says about VPCMPUB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

• Vectors and floating point: An AVX-512 compare that writes a mask register, such as VPCMPD, takes 3, 4 or 5 cycles for 128, 256 or 512 bits, where the older compares into a vector register take one cycle for integers and two for floats. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    a = zmm2.b[i]
    b = src3.b[i]
    k1[i] = k2[i] and compare(imm8, a, b)
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 false, 4 !=, 5 >=, 6 >, 7 true
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPCMPUB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPBLENDMQ
• VPBLENDMW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTMB2Q
• VPBROADCASTMW2D
• VPBROADCASTQ
• VPBROADCASTW
• VPCLMULQDQ
• VPCMPB
• VPCMPD
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPQ
• VPCMPUD
• VPCMPUQ
• VPCMPUW
• VPCMPW
• VPCOMPRESSB
• VPCOMPRESSD
• VPCOMPRESSQ
• VPCOMPRESSW
• VPCONFLICTD
• VPCONFLICTQ
• VPDPBUSD
• VPDPBUSDS
• VPDPWSSD
• VPDPWSSDS
• VPERMB
• VPERMD
• VPERMI2B
• VPERMI2D
• VPERMI2PD
• VPERMI2PS

All 686 AVX10.1 instructions